use internal clock

[raggedstone] / heartbeat / source / top_raggedstone.vhd

diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd
index b0739895d536833d7a1a5db286d478bb755cade8..01dc26bde0fa09934f30768c7fa92d81b809dbfb 100644 (file)
--- a/heartbeat/source/top_raggedstone.vhd
+++ b/heartbeat/source/top_raggedstone.vhd
@@ -44,6 +44,7 @@ port (
     -- General \r
     PCI_CLK     : in std_logic;\r
     PCI_nRES    : in std_logic;\r
+    PCI_nREQ    : out std_logic;\r
     \r
     -- PCI target 32bits\r
     PCI_AD      : inout std_logic_vector(31 downto 0);\r
@@ -64,6 +65,10 @@ port (
        LED2    : out std_logic;\r
        LED4            : out std_logic;\r
        LED5            : out std_logic\r
+--     IDE1    : out std_logic;\r
+--     IDE2    : out std_logic;\r
+--     IDE3    : out std_logic;\r
+--     IDE4    : out std_logic\r
 \r
 );\r
 end raggedstone;\r
@@ -127,7 +132,11 @@ port (
        led2_o : out std_logic;\r
        led3_o : out std_logic;\r
        led4_o : out std_logic;\r
-       led5_o : out std_logic\r
+       led5_o : out std_logic;\r
+       led6_o : out std_logic;\r
+       led7_o : out std_logic;\r
+       led8_o : out std_logic;\r
+       led9_o : out std_logic\r
 );\r
 end component;\r
 \r
@@ -153,6 +162,8 @@ end component;
 \r
 begin\r
 \r
+       PCI_nREQ <= '1';\r
+\r
 --+-----------------------------------------+\r
 --|  PCI Target                                                        |\r
 --+-----------------------------------------+\r
@@ -199,6 +210,10 @@ port map(
        led3_o => LED3,\r
        led4_o => LED4,\r
        led5_o => LED5\r
+--     led6_o => IDE1,\r
+--     led7_o => IDE2,\r
+--     led8_o => IDE3,\r
+--     led9_o => IDE4\r
 );\r
 \r
 end raggedstone_arch;\r