--- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007\r
-\r
-\r
-\r
-LIBRARY ieee;\r
-\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-\r
-entity FIFO_CONTROL is\r
- Port ( FIFO_RDn : In std_logic;\r
- FLAG_IN_0 : In std_logic;\r
- FLAG_IN_4 : In std_logic;\r
- HOLD : In std_logic;\r
- KONST_1 : In std_logic;\r
- PCI_CLOCK : In std_logic;\r
- PSC_ENABLE : In std_logic;\r
- R_EFn : In std_logic;\r
- R_FFn : In std_logic;\r
- R_HFn : In std_logic;\r
- RESET : In std_logic;\r
- S_EFn : In std_logic;\r
- S_FFn : In std_logic;\r
- S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
- S_HFn : In std_logic;\r
- SERIAL_IN : In std_logic;\r
- SPC_ENABLE : In std_logic;\r
- SPC_RDY_IN : In std_logic;\r
- WRITE_XX1_0 : In std_logic;\r
- R_ERROR : Out std_logic;\r
- R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
- R_FIFO_READn : Out std_logic;\r
- R_FIFO_RESETn : Out std_logic;\r
- R_FIFO_RETRANSMITn : Out std_logic;\r
- R_FIFO_WRITEn : Out std_logic;\r
- RESERVE : Out std_logic;\r
- S_ERROR : Out std_logic;\r
- S_FIFO_READn : Out std_logic;\r
- S_FIFO_RESETn : Out std_logic;\r
- S_FIFO_RETRANSMITn : Out std_logic;\r
- S_FIFO_WRITEn : Out std_logic;\r
- SERIAL_OUT : Out std_logic;\r
- SPC_RDY_OUT : Out std_logic;\r
- SR_ERROR : Out std_logic;\r
- SYNC_FLAG : Out std_logic_vector (7 downto 0);\r
- PAR_SER_IN : Out std_logic_vector (7 downto 0);\r
- SER_PAR_OUT : Out std_logic_vector (7 downto 0));\r
-end FIFO_CONTROL;\r
-\r
-architecture SCHEMATIC of FIFO_CONTROL is\r
-\r
- SIGNAL gnd : std_logic := '0';\r
- SIGNAL vcc : std_logic := '1';\r
-\r
- signal XXXR_FIFO_WRITEn : std_logic;\r
- signal XXXS_FIFO_READn : std_logic;\r
- signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);\r
- signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);\r
- signal watcher : std_logic_vector (7 downto 0);\r
-\r
- component SER_PAR_CON\r
- Port ( PCI_CLOCK : In std_logic;\r
- RESET : In std_logic;\r
- SERIAL_IN : In std_logic;\r
- SPC_ENABLE : In std_logic;\r
- SYNC_R_FIFO_FFn : In std_logic;\r
- PAR_OUT : Out std_logic_vector (7 downto 0);\r
- R_FIFO_WRITEn : Out std_logic;\r
- SPC_RDY_OUT : Out std_logic );\r
- end component;\r
-\r
- component PAR_SER_CON\r
- Port ( PAR_IN : In std_logic_vector (7 downto 0);\r
- PCI_CLOCK : In std_logic;\r
- PSC_ENABLE : In std_logic;\r
- RESET : In std_logic;\r
- SPC_RDY_IN : In std_logic;\r
- SYNC_S_FIFO_EFn : In std_logic;\r
- S_FIFO_READn : Out std_logic;\r
- SER_OUT : Out std_logic );\r
- end component;\r
-\r
- component FIFO_IO_CONTROL\r
- Port ( FIFO_RDn : In std_logic;\r
- PCI_CLOCK : In std_logic;\r
- RESET : In std_logic;\r
- SYNC_FLAG_1 : In std_logic;\r
- SYNC_FLAG_7 : In std_logic;\r
- WRITE_XX1_0 : In std_logic;\r
- R_ERROR : Out std_logic;\r
- R_FIFO_READn : Out std_logic;\r
- R_FIFO_RESETn : Out std_logic;\r
- R_FIFO_RETRANSMITn : Out std_logic;\r
- S_ERROR : Out std_logic;\r
- S_FIFO_RESETn : Out std_logic;\r
- S_FIFO_RETRANSMITn : Out std_logic;\r
- S_FIFO_WRITEn : Out std_logic;\r
- SR_ERROR : Out std_logic );\r
- end component;\r
-\r
- component CONNECTING_FSM\r
- Port ( PCI_CLOCK : In std_logic;\r
- PSC_ENABLE : In std_logic;\r
- RESET : In std_logic;\r
- S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
- SPC_ENABLE : In std_logic;\r
- SYNC_R_FIFO_FFn : In std_logic;\r
- SYNC_S_FIFO_EFn : In std_logic;\r
- R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
- R_FIFO_WRITEn : Out std_logic;\r
- S_FIFO_READn : Out std_logic );\r
- end component;\r
-\r
- component FLAG_BUS\r
- Port ( FLAG_IN_0 : In std_logic;\r
- FLAG_IN_4 : In std_logic;\r
- HOLD : In std_logic;\r
- KONS_1 : In std_logic;\r
- PCI_CLOCK : In std_logic;\r
- R_EFn : In std_logic;\r
- R_FFn : In std_logic;\r
- R_HFn : In std_logic;\r
- S_EFn : In std_logic;\r
- S_FFn : In std_logic;\r
- S_HFn : In std_logic;\r
- SYNC_FLAG : Out std_logic_vector (7 downto 0) );\r
- end component;\r
-\r
-begin\r
-\r
- SYNC_FLAG <= SYNC_FLAG_DUMMY;\r
- PAR_SER_IN <= S_FIFO_Q_OUT;\r
- SER_PAR_OUT <= watcher;\r
- R_FIFO_D_IN(7 downto 0) <= watcher;\r
-\r
- RESERVE <= gnd;\r
- I23 : SER_PAR_CON\r
- Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
- SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,\r
- SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
- PAR_OUT(7 downto 0)=>watcher,\r
- R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );\r
- I22 : PAR_SER_CON\r
- Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
- PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
- RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN,\r
- SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
- S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT );\r
- I21 : FIFO_IO_CONTROL\r
- Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
- SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1),\r
- SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7),\r
- WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
- R_FIFO_READn=>R_FIFO_READn,\r
- R_FIFO_RESETn=>R_FIFO_RESETn,\r
- R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn,\r
- S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn,\r
- S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn,\r
- S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR );\r
- I20 : CONNECTING_FSM\r
- Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
- RESET=>RESET,\r
- S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
- SPC_ENABLE=>SPC_ENABLE,\r
- SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
- SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
- R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0),\r
- R_FIFO_WRITEn=>XXXR_FIFO_WRITEn,\r
- S_FIFO_READn=>XXXS_FIFO_READn );\r
- I19 : FLAG_BUS\r
- Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD,\r
- KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn,\r
- R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn,\r
- S_HFn=>S_HFn,\r
- SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) );\r
-\r
-end SCHEMATIC;\r
+-- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007
+
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity FIFO_CONTROL is
+ Port ( FIFO_RDn : In std_logic;
+ FLAG_IN_0 : In std_logic;
+ FLAG_IN_4 : In std_logic;
+ HOLD : In std_logic;
+ KONST_1 : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PSC_ENABLE : In std_logic;
+ R_EFn : In std_logic;
+ R_FFn : In std_logic;
+ R_HFn : In std_logic;
+ RESET : In std_logic;
+ S_EFn : In std_logic;
+ S_FFn : In std_logic;
+ S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
+ S_HFn : In std_logic;
+ SERIAL_IN : In std_logic;
+ SPC_ENABLE : In std_logic;
+ SPC_RDY_IN : In std_logic;
+ WRITE_XX1_0 : In std_logic;
+ R_ERROR : Out std_logic;
+ R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
+ R_FIFO_READn : Out std_logic;
+ R_FIFO_RESETn : Out std_logic;
+ R_FIFO_RETRANSMITn : Out std_logic;
+ R_FIFO_WRITEn : Out std_logic;
+ RESERVE : Out std_logic;
+ S_ERROR : Out std_logic;
+ S_FIFO_READn : Out std_logic;
+ S_FIFO_RESETn : Out std_logic;
+ S_FIFO_RETRANSMITn : Out std_logic;
+ S_FIFO_WRITEn : Out std_logic;
+ SERIAL_OUT : Out std_logic;
+ SPC_RDY_OUT : Out std_logic;
+ SR_ERROR : Out std_logic;
+ SYNC_FLAG : Out std_logic_vector (7 downto 0));
+end FIFO_CONTROL;
+
+architecture SCHEMATIC of FIFO_CONTROL is
+
+ SIGNAL gnd : std_logic := '0';
+ SIGNAL vcc : std_logic := '1';
+
+ signal XXXR_FIFO_WRITEn : std_logic;
+ signal XXXS_FIFO_READn : std_logic;
+ signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);
+ signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);
+
+ component SER_PAR_CON
+ Port ( PCI_CLOCK : In std_logic;
+ RESET : In std_logic;
+ SERIAL_IN : In std_logic;
+ SPC_ENABLE : In std_logic;
+ SYNC_R_FIFO_FFn : In std_logic;
+ PAR_OUT : Out std_logic_vector (7 downto 0);
+ R_FIFO_WRITEn : Out std_logic;
+ SPC_RDY_OUT : Out std_logic );
+ end component;
+
+ component PAR_SER_CON
+ Port ( PAR_IN : In std_logic_vector (7 downto 0);
+ PCI_CLOCK : In std_logic;
+ PSC_ENABLE : In std_logic;
+ RESET : In std_logic;
+ SPC_RDY_IN : In std_logic;
+ SYNC_S_FIFO_EFn : In std_logic;
+ S_FIFO_READn : Out std_logic;
+ SER_OUT : Out std_logic );
+ end component;
+
+ component FIFO_IO_CONTROL
+ Port ( FIFO_RDn : In std_logic;
+ PCI_CLOCK : In std_logic;
+ RESET : In std_logic;
+ SYNC_FLAG_1 : In std_logic;
+ SYNC_FLAG_7 : In std_logic;
+ WRITE_XX1_0 : In std_logic;
+ R_ERROR : Out std_logic;
+ R_FIFO_READn : Out std_logic;
+ R_FIFO_RESETn : Out std_logic;
+ R_FIFO_RETRANSMITn : Out std_logic;
+ S_ERROR : Out std_logic;
+ S_FIFO_RESETn : Out std_logic;
+ S_FIFO_RETRANSMITn : Out std_logic;
+ S_FIFO_WRITEn : Out std_logic;
+ SR_ERROR : Out std_logic );
+ end component;
+
+ component CONNECTING_FSM
+ Port ( PCI_CLOCK : In std_logic;
+ PSC_ENABLE : In std_logic;
+ RESET : In std_logic;
+ S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
+ SPC_ENABLE : In std_logic;
+ SYNC_R_FIFO_FFn : In std_logic;
+ SYNC_S_FIFO_EFn : In std_logic;
+ R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
+ R_FIFO_WRITEn : Out std_logic;
+ S_FIFO_READn : Out std_logic );
+ end component;
+
+ component FLAG_BUS
+ Port ( FLAG_IN_0 : In std_logic;
+ FLAG_IN_4 : In std_logic;
+ HOLD : In std_logic;
+ KONS_1 : In std_logic;
+ PCI_CLOCK : In std_logic;
+ R_EFn : In std_logic;
+ R_FFn : In std_logic;
+ R_HFn : In std_logic;
+ S_EFn : In std_logic;
+ S_FFn : In std_logic;
+ S_HFn : In std_logic;
+ SYNC_FLAG : Out std_logic_vector (7 downto 0) );
+ end component;
+
+begin
+
+ SYNC_FLAG <= SYNC_FLAG_DUMMY;
+
+ RESERVE <= gnd;
+ I23 : SER_PAR_CON
+ Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
+ SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,
+ SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
+ PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
+ R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );
+ I22 : PAR_SER_CON
+ Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
+ PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,
+ RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN,
+ SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),
+ S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT );
+ I21 : FIFO_IO_CONTROL
+ Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
+ SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1),
+ SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7),
+ WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
+ R_FIFO_READn=>R_FIFO_READn,
+ R_FIFO_RESETn=>R_FIFO_RESETn,
+ R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn,
+ S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn,
+ S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn,
+ S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR );
+ I20 : CONNECTING_FSM
+ Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,
+ RESET=>RESET,
+ S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
+ SPC_ENABLE=>SPC_ENABLE,
+ SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
+ SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),
+ R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0),
+ R_FIFO_WRITEn=>XXXR_FIFO_WRITEn,
+ S_FIFO_READn=>XXXS_FIFO_READn );
+ I19 : FLAG_BUS
+ Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD,
+ KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn,
+ R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn,
+ S_HFn=>S_HFn,
+ SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) );
+
+end SCHEMATIC;
projects / raggedstone / blobdiff