X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/097d51b95594ff356620de1247efaf47fa11736c..f822acebac284df723c5196d47295f447c5338df:/dhwk/source/top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index e2f307c..2d25fcd 100644
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -170,6 +170,7 @@ architecture SCHEMATIC of dhwk is
              SPC_RDY_OUT : Out   std_logic;
              SR_ERROR : Out   std_logic;
 	     PAR_SER_IN : Out std_logic_vector (7 downto 0);
+	     SER_PAR_OUT : Out std_logic_vector (7 downto 0);
              SYNC_FLAG : Out   std_logic_vector (7 downto 0) );
    end component;
 
@@ -251,7 +252,7 @@ begin
 	LED_4 <= '0';
 	LED_5 <= not watch;
 	PCI_INTAn <= watch;
-	trig0(7 downto 0) <= (0 => watch, others => '0');
+	trig0(7 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');
 	data(0) <= watch;
 	
 	data(1) <= R_EFn;
@@ -272,6 +273,7 @@ begin
 	data(16) <= SPC_RDY_IN;
 	data(17) <= SERIAL_OUT;
 	data(18) <= SPC_RDY_OUT;
+	data(34 downto 27) <= R_FIFO_Q_OUT;
 
    I19 : MESS_1_TB
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,