X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/0b6ed0d89260ade25dc0c2dc9fb8aa154fabd6a1..30273618403fd6512926c89f999f97b4722e1709:/dhwk/source/MESS_1_TB.vhd

diff --git a/dhwk/source/MESS_1_TB.vhd b/dhwk/source/MESS_1_TB.vhd
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--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 29.08.2006
--- File: MESS_1_TB.VHD
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity MESS_1_TB is
-        port
-        (
-                KONST_1 :in std_logic;
-                PCI_IDSEL :in std_logic;
-                DEVSELn :in std_logic;
-                INTAn :in std_logic;
-                REG_OUT_XX7 :in std_logic_vector(7 downto 0);
-                TB_PCI_IDSEL :out std_logic;
-                TB_DEVSELn :out std_logic;
-                TB_INTAn :out std_logic
-        );
-end entity MESS_1_TB;
-
-architecture MESS_1_TB_DESIGN of MESS_1_TB is
-
-begin
-
-        TB_PCI_IDSEL <= PCI_IDSEL and KONST_1;
-
-        TB_INTAn <= INTAn and KONST_1;
-
-        TB_DEVSELn <= DEVSELn when REG_OUT_XX7(7) = '0' else (not REG_OUT_XX7(6));
-
-end architecture MESS_1_TB_DESIGN;