X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/0b6ed0d89260ade25dc0c2dc9fb8aa154fabd6a1..30273618403fd6512926c89f999f97b4722e1709:/dhwk/source/pci/comm_fsm.vhd

diff --git a/dhwk/source/pci/comm_fsm.vhd b/dhwk/source/pci/comm_fsm.vhd
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+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: COMM_FSM.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity COMM_FSM is
+        port
+        (
+                PCI_CLOCK :in std_logic;
+                PCI_RSTn :in std_logic;
+                IO_READ :in std_logic;
+                IO_WRITE :in std_logic;
+                CONF_READ :in std_logic;
+                CONF_WRITE :in std_logic;
+                DEVSELn :in std_logic;
+
+                IO_RD_COM : out std_logic;--> MUX_SEL(0)
+                CF_RD_COM :out std_logic;
+                IO_WR_COM :out std_logic;
+                CF_WR_COM :out std_logic
+        );
+end entity COMM_FSM;
+
+architecture COMM_FSM_DESIGN of COMM_FSM is
+
+
+ --**********************************************************
+ --*** COMMAND FSM CODIERUNG ***
+ --**********************************************************
+ --
+ --
+ -- |--------- IO_RD_COM
+ -- ||-------- CF_RD_COM
+ -- |||------- IO_WR_COM
+ -- ||||------ CF_WR_COM
+ -- ||||
+        constant ST_IDLE_COMM :std_logic_vector (3 downto 0) := "0000";--
+        constant ST_CONF_WRITE :std_logic_vector (3 downto 0) := "0001";--
+        constant ST_IO_WRITE :std_logic_vector (3 downto 0) := "0010";--
+        constant ST_CONF_READ :std_logic_vector (3 downto 0) := "0100";--
+        constant ST_IO_READ :std_logic_vector (3 downto 0) := "1000";--
+
+        signal COMM_STATE :std_logic_vector (3 downto 0);
+
+ --************************************************************
+ --*** FSM SPEICHER-AUTOMAT ***
+ --************************************************************
+
+        attribute syn_state_machine : boolean;
+        attribute syn_state_machine of COMM_STATE : signal is false;
+
+begin
+
+ --**********************************************************
+ --*** COMMAND FSM ***
+ --**********************************************************
+
+        process (PCI_CLOCK, PCI_RSTn)
+        begin
+        if PCI_RSTn = '0' then
+                COMM_STATE <= "0000";
+
+        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                case COMM_STATE is
+                when ST_IDLE_COMM =>
+                        if IO_READ = '1' then COMM_STATE <= ST_IO_READ;
+
+                        elsif CONF_READ = '1' then
+                                COMM_STATE <= ST_CONF_READ;
+
+                        elsif IO_WRITE = '1' then
+                                COMM_STATE <= ST_IO_WRITE;
+
+                        elsif CONF_WRITE = '1' then
+                                COMM_STATE <= ST_CONF_WRITE;
+
+                        else
+                                COMM_STATE <= ST_IDLE_COMM;
+                        end if;
+
+                when ST_IO_READ =>
+                        if DEVSELn = '1' then
+                                COMM_STATE <= ST_IDLE_COMM;
+                        end if;
+
+                when ST_CONF_READ =>
+                        if DEVSELn = '1' then
+                                COMM_STATE <= ST_IDLE_COMM;
+                        end if;
+
+                when ST_IO_WRITE =>
+                        if DEVSELn = '1' then
+                                COMM_STATE <= ST_IDLE_COMM;
+                        end if;
+
+                when ST_CONF_WRITE =>
+                        if DEVSELn = '1' then
+                                COMM_STATE <= ST_IDLE_COMM;
+                        end if;
+
+                when others =>
+                        COMM_STATE <= ST_IDLE_COMM;
+
+                end case; -- COMM_STATE
+        end if; -- CLOCK
+end process; -- PROCESS
+
+ IO_RD_COM <= COMM_STATE(3);
+ CF_RD_COM <= COMM_STATE(2);
+ IO_WR_COM <= COMM_STATE(1);
+ CF_WR_COM <= COMM_STATE(0);
+
+end architecture COMM_FSM_DESIGN;