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+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: PARITY_4.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity PARITY_4 is
+        port
+        (
+                PAR_IN :in std_logic_vector(3 downto 0);
+                PAR_OUT :out std_logic
+        );
+end entity PARITY_4;
+
+architecture PARITY_4_DESIGN of PARITY_4 is
+
+begin
+
+        PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0);
+
+end architecture PARITY_4_DESIGN;