X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/0b6ed0d89260ade25dc0c2dc9fb8aa154fabd6a1..e90b12fe13402c4c3e6935acf0b09fedecf18fd0:/dhwk/source/pci/config_space_header.vhd diff --git a/dhwk/source/pci/config_space_header.vhd b/dhwk/source/pci/config_space_header.vhd index 15db761..0cd1420 100644 --- a/dhwk/source/pci/config_space_header.vhd +++ b/dhwk/source/pci/config_space_header.vhd @@ -27,6 +27,10 @@ end CONFIG_SPACE_HEADER; architecture SCHEMATIC of CONFIG_SPACE_HEADER is + constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE"; + --other comm. device + constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000"; + SIGNAL gnd : std_logic := '0'; SIGNAL vcc : std_logic := '1'; @@ -84,16 +88,6 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is CONF_DATA_10H : Out std_logic_vector (31 downto 0) ); end component; - component CONFIG_08H - Port ( REVISION_ID : In std_logic_vector (7 downto 0); - CONF_DATA_08H : Out std_logic_vector (31 downto 0) ); - end component; - - component CONFIG_00H - Port ( VENDOR_ID : In std_logic_vector (15 downto 0); - CONF_DATA_00H : Out std_logic_vector (31 downto 0) ); - end component; - component CONFIG_04H Port ( AD_REG : In std_logic_vector (31 downto 0); CBE_REGn : In std_logic_vector (3 downto 0); @@ -106,6 +100,8 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is end component; begin + CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID; + CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID; CONF_DATA_04H <= CONF_DATA_04H_DUMMY; CONF_DATA_10H <= CONF_DATA_10H_DUMMY; @@ -139,12 +135,6 @@ begin CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn, CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) ); - I4 : CONFIG_08H - Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0), - CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) ); - I3 : CONFIG_00H - Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0), - CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) ); I2 : CONFIG_04H Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0), CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),