X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/0de2df9caee0439ffcd042c82921a4e4753de8c3..2d8e1276d2533e26fcbc241b34dcc0af17eed492:/dhwk_old/source/top_dhwk.vhd

diff --git a/dhwk_old/source/top_dhwk.vhd b/dhwk_old/source/top_dhwk.vhd
index 67fe5aa..accd1a3 100644
--- a/dhwk_old/source/top_dhwk.vhd
+++ b/dhwk_old/source/top_dhwk.vhd
@@ -109,34 +109,37 @@ port (
 );
 end component;
 
-component generic_dpram
+component wb_7seg_new
 port (
-	rclk		: in std_logic;
-	rrst		: in std_logic;
-	rce		: in std_logic;
-	oe		: in std_logic;
-	raddr		: in std_logic_vector(11 downto 0);
-	do		: out std_logic_vector(7 downto 0);
-	wclk		: in std_logic;
-	wrst		: in std_logic;
-	wce		: in std_logic;
-	we		: in std_logic;
-	waddr		: in std_logic_vector(11 downto 0);
-	di		: in std_logic_vector(7 downto 0)
+	clk_i		: in std_logic;
+	nrst_i		: in std_logic;
+	
+	wb_adr_i	: in std_logic_vector(24 downto 1);
+	wb_dat_o	: out std_logic_vector(15 downto 0);
+	wb_dat_i	: in std_logic_vector(15 downto 0);
+	wb_sel_i	: in std_logic_vector(1 downto 0);
+	wb_we_i		: in std_logic;
+	wb_stb_i	: in std_logic;
+	wb_cyc_i	: in std_logic;
+	wb_ack_o	: out std_logic;
+	wb_err_o	: out std_logic;
+	wb_int_o	: out std_logic;
+	
+	DISP_SEL	: inout std_logic_vector(3 downto 0);
+	DISP_LED	: out std_logic_vector(6 downto 0)
 );
 end component;
 
-
-	signal 	wb_adr :		std_logic_vector(24 downto 1);   
-	signal	wb_dat_out :	std_logic_vector(15 downto 0);
- 	signal 	wb_dat_in :		std_logic_vector(15 downto 0);
-	signal	wb_sel :		std_logic_vector(1 downto 0);
- 	signal  wb_we :			std_logic;
-	signal	wb_stb :		std_logic;
-	signal	wb_cyc :		std_logic;
-	signal	wb_ack :		std_logic;
-	signal	wb_err :		std_logic;
-	signal	wb_int :		std_logic;
+signal 	wb_adr :		std_logic_vector(24 downto 1);   
+signal	wb_dat_out :	std_logic_vector(15 downto 0);
+signal 	wb_dat_in :		std_logic_vector(15 downto 0);
+signal	wb_sel :		std_logic_vector(1 downto 0);
+signal  wb_we :			std_logic;
+signal	wb_stb :		std_logic;
+signal	wb_cyc :		std_logic;
+signal	wb_ack :		std_logic;
+signal	wb_err :		std_logic;
+signal	wb_int :		std_logic;
 
 
 begin