X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/152884e67f2cea6ff9f5787eab6c72dcffe484e4..816293e0b569a4cb30f94f8f9dacfb721039ed1d:/heartbeat/source/top_raggedstone.vhd?ds=inline

diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd
index 73fefb1..3d369cf 100644
--- a/heartbeat/source/top_raggedstone.vhd
+++ b/heartbeat/source/top_raggedstone.vhd
@@ -38,12 +38,13 @@ use ieee.std_logic_unsigned.all;
 --|									ENTITY   									|
 --+-----------------------------------------------------------------------------+
 
-entity pci_7seg is
+entity raggedstone is
 port (
 
     -- General 
     PCI_CLK     : in std_logic;
     PCI_nRES    : in std_logic;
+    PCI_nREQ    : out std_logic;
     
     -- PCI target 32bits
     PCI_AD      : inout std_logic_vector(31 downto 0);
@@ -60,19 +61,24 @@ port (
     PCI_nINT    : out std_logic;
  
 	-- debug signals
-	LED_INIT	 : out std_logic;
-	LED_ACCESS	 : out std_logic;
-	LED_ALIVE : out std_logic
+	LED3	: out std_logic;
+	LED2	: out std_logic;
+	LED4		: out std_logic;
+	LED5		: out std_logic;
+	IDE1	: out std_logic;
+	IDE2	: out std_logic;
+	IDE3	: out std_logic;
+	IDE4	: out std_logic
 
 );
-end pci_7seg;
+end raggedstone;
 
 
 --+-----------------------------------------------------------------------------+
 --|									ARCHITECTURE								|
 --+-----------------------------------------------------------------------------+
 
-architecture pci_7seg_arch of pci_7seg is
+architecture raggedstone_arch of raggedstone is
 
 
 --+-----------------------------------------------------------------------------+
@@ -123,7 +129,14 @@ component heartbeat
 port (
 	clk_i : in std_logic;
 	nrst_i : in std_logic;
-	led_o : out std_logic
+	led2_o : out std_logic;
+	led3_o : out std_logic;
+	led4_o : out std_logic;
+	led5_o : out std_logic;
+	led6_o : out std_logic;
+	led7_o : out std_logic;
+	led8_o : out std_logic;
+	led9_o : out std_logic
 );
 end component;
 
@@ -149,6 +162,8 @@ end component;
 
 begin
 
+	PCI_nREQ <= '1';
+
 --+-----------------------------------------+
 --|  PCI Target 							|
 --+-----------------------------------------+
@@ -178,9 +193,9 @@ port map(
 		wb_cyc_o =>		wb_cyc,
 		wb_ack_i =>		wb_ack,
 		wb_err_i =>		wb_err,
-		wb_int_i =>		wb_int,
-		debug_init =>	LED_INIT,
-		debug_access =>	LED_ACCESS
+		wb_int_i =>		wb_int
+--		debug_init =>	LED3,
+--		debug_access =>	LED2
 		);
 
 --+-----------------------------------------+
@@ -191,7 +206,14 @@ my_heartbeat: component heartbeat
 port map( 
 	clk_i => PCI_CLK,
 	nrst_i => PCI_nRES,
-	led_o => LED_ALIVE
+	led2_o => LED2,
+	led3_o => LED3,
+	led4_o => LED4,
+	led5_o => LED5,
+	led6_o => IDE1,
+	led7_o => IDE2,
+	led8_o => IDE3,
+	led9_o => IDE4
 );
 
-end pci_7seg_arch;
+end raggedstone_arch;