X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/1afff8d481bb2d34c54b1c669b400bf706a9e7b6..8985684ba1f0b0006387e6a45ec44f684bce0d36:/dhwk/source/top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index dda8be1..971b0c4 100644
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -92,8 +92,8 @@ architecture SCHEMATIC of dhwk is
    signal SPC_RDY_OUT : std_logic;
    signal watch : std_logic;
    signal control0       : std_logic_vector(35 downto 0);
-   signal data       : std_logic_vector(63 downto 0);
-   signal trig0      : std_logic_vector(7 downto 0);
+   signal data       : std_logic_vector(95 downto 0);
+   signal trig0      : std_logic_vector(31 downto 0);
 
    component MESS_1_TB
       Port ( DEVSELn : In    std_logic;
@@ -236,8 +236,8 @@ end component;
     (
       control     : in    std_logic_vector(35 downto 0);
       clk         : in    std_logic;
-      data        : in    std_logic_vector(63 downto 0);
-      trig0       : in    std_logic_vector(7 downto 0)
+      data        : in    std_logic_vector(95 downto 0);
+      trig0       : in    std_logic_vector(31 downto 0)
     );
   end component;
 
@@ -250,28 +250,31 @@ begin
 	LED_4 <= '0';
 	LED_5 <= not watch;
 	PCI_INTAn <= watch;
-	trig0(7 downto 0) <= (others => '0');
-	data(31 downto 0) <= PCI_AD(31 downto 0);
-	data(32) <= watch;
+	trig0(31 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');
+	data(0) <= watch;
 	
-	data(33) <= R_EFn;
-	data(34) <= R_HFn;
-	data(35) <= R_FFn;
-	data(36) <= R_FIFO_READn;
-	data(37) <= R_FIFO_RESETn;
-	data(38) <= R_FIFO_RTn;
-	data(39) <= R_FIFO_WRITEn;
-	data(40) <= S_EFn;
-	data(41) <= S_HFn;
-	data(42) <= S_FFn;
-	data(43) <= S_FIFO_READn;
-	data(44) <= S_FIFO_RESETn;
-	data(45) <= S_FIFO_RTn;
-	data(46) <= S_FIFO_WRITEn;
-	data(47) <= SERIAL_IN;
-	data(48) <= SPC_RDY_IN;
-	data(49) <= SERIAL_OUT;
-	data(50) <= SPC_RDY_OUT;
+	data(1) <= R_EFn;
+	data(2) <= R_HFn;
+	data(3) <= R_FFn;
+	data(4) <= R_FIFO_READn;
+	data(5) <= R_FIFO_RESETn;
+	data(6) <= R_FIFO_RTn;
+	data(7) <= R_FIFO_WRITEn;
+	data(8) <= S_EFn;
+	data(9) <= S_HFn;
+	data(10) <= S_FFn;
+	data(11) <= S_FIFO_READn;
+	data(12) <= S_FIFO_RESETn;
+	data(13) <= S_FIFO_RTn;
+	data(14) <= S_FIFO_WRITEn;
+	data(15) <= SERIAL_IN;
+	data(16) <= SPC_RDY_IN;
+	data(17) <= SERIAL_OUT;
+	data(18) <= SPC_RDY_OUT;
+	data(26 downto 19) <= S_FIFO_Q_OUT;
+	data(34 downto 27) <= R_FIFO_Q_OUT;
+	data(66 downto 35) <= PCI_AD(31 downto 0);
+	data(70 downto 67) <= PCI_CBEn(3 downto 0);
 
    I19 : MESS_1_TB
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,