X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/1d175e4f030e4cee19ec6df3b39bfad3bf64863c..1cc8dbebf4ad3ef2d28da957b2830483b2089452:/dhwk/source/top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index 4becb68..5258c3a 100644
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -92,8 +92,8 @@ architecture SCHEMATIC of dhwk is
    signal SPC_RDY_OUT : std_logic;
    signal watch : std_logic;
    signal control0       : std_logic_vector(35 downto 0);
-   signal data       : std_logic_vector(35 downto 0);
-   signal trig0      : std_logic_vector(7 downto 0);
+   signal data       : std_logic_vector(95 downto 0);
+   signal trig0      : std_logic_vector(31 downto 0);
 
    component MESS_1_TB
       Port ( DEVSELn : In    std_logic;
@@ -236,8 +236,8 @@ end component;
     (
       control     : in    std_logic_vector(35 downto 0);
       clk         : in    std_logic;
-      data        : in    std_logic_vector(35 downto 0);
-      trig0       : in    std_logic_vector(7 downto 0)
+      data        : in    std_logic_vector(95 downto 0);
+      trig0       : in    std_logic_vector(31 downto 0)
     );
   end component;
 
@@ -250,7 +250,7 @@ begin
 	LED_4 <= '0';
 	LED_5 <= not watch;
 	PCI_INTAn <= watch;
-	trig0(7 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');
+	trig0(31 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');
 	data(0) <= watch;
 	
 	data(1) <= R_EFn;
@@ -273,6 +273,7 @@ begin
 	data(18) <= SPC_RDY_OUT;
 	data(26 downto 19) <= S_FIFO_Q_OUT;
 	data(34 downto 27) <= R_FIFO_Q_OUT;
+	data(66 downto 35) <= PCI_AD(31 downto 0);
 
    I19 : MESS_1_TB
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,