X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/221bd70b5503765fbe6b3e350d7ec5dee80bd8e8..HEAD:/ethernet/source/top.vhd diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd index 0541222..899bc12 100644 --- a/ethernet/source/top.vhd +++ b/ethernet/source/top.vhd @@ -1,5 +1,7 @@ LIBRARY ieee; USE ieee.std_logic_1164.ALL; +Library UNISIM; +use UNISIM.vcomponents.all; entity ethernet is PORT( @@ -30,7 +32,11 @@ PORT( MCOLL_PAD_I : IN std_logic; MCRS_PAD_I : IN std_logic; MD_PAD_IO : INOUT std_logic; - MDC_PAD_O : OUT std_logic + MDC_PAD_O : OUT std_logic; + + PHY_CLOCK : OUT std_logic; + + LED_2 : OUT std_logic ); end ethernet; @@ -72,6 +78,8 @@ PORT( mdc_pad_o : OUT std_logic; md_pad_o : OUT std_logic; md_padoe_o : OUT std_logic; + m_wb_cti_o : OUT std_logic_vector(2 downto 0); + m_wb_bte_o : OUT std_logic_vector(1 downto 0); int_o : OUT std_logic ); END COMPONENT; @@ -150,31 +158,66 @@ PORT( ); END COMPONENT; +component icon +port ( + control0 : out std_logic_vector(35 downto 0) + ); +end component; + +component ila +port ( + control : in std_logic_vector(35 downto 0); + clk : in std_logic; + data : in std_logic_vector(63 downto 0); + trig0 : in std_logic_vector(31 downto 0) + ); +end component; + +component phydcm is +port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end component; + +signal pci_rst_i : std_logic; signal pci_rst_o : std_logic; signal pci_rst_oe_o : std_logic; +signal pci_inta_i : std_logic; signal pci_inta_o : std_logic; signal pci_inta_oe_o : std_logic; signal pci_req_o : std_logic; signal pci_req_oe_o : std_logic; +signal pci_frame_i : std_logic; signal pci_frame_o : std_logic; signal pci_frame_oe_o : std_logic; +signal pci_irdy_i : std_logic; signal pci_irdy_o : std_logic; signal pci_irdy_oe_o : std_logic; +signal pci_devsel_i : std_logic; signal pci_devsel_o : std_logic; signal pci_devsel_oe_o : std_logic; +signal pci_trdy_i : std_logic; signal pci_trdy_o : std_logic; signal pci_trdy_oe_o : std_logic; +signal pci_stop_i : std_logic; signal pci_stop_o : std_logic; signal pci_stop_oe_o : std_logic; +signal pci_par_i : std_logic; signal pci_par_o : std_logic; signal pci_par_oe_o : std_logic; +signal pci_perr_i : std_logic; signal pci_perr_o : std_logic; signal pci_perr_oe_o : std_logic; +signal pci_serr_i : std_logic; signal pci_serr_o : std_logic; signal pci_serr_oe_o : std_logic; signal pci_ad_oe_o : std_logic_vector(31 downto 0); signal pci_cbe_oe_o : std_logic_vector(3 downto 0); +signal pci_ad_i : std_logic_vector (31 downto 0); signal pci_ad_o : std_logic_vector (31 downto 0); +signal pci_cbe_i : std_logic_vector (3 downto 0); signal pci_cbe_o : std_logic_vector (3 downto 0); signal wb_clk_i : std_logic; @@ -197,35 +240,150 @@ signal m_wb_cyc_o : std_logic; signal m_wb_stb_o : std_logic; signal m_wb_ack_i : std_logic; signal m_wb_err_i : std_logic; +signal md_pad_i : std_logic; signal md_pad_o : std_logic; signal md_padoe_o : std_logic; signal int_o : std_logic; signal wbm_adr_o : std_logic_vector(31 downto 0); +signal mdc_pad_o_watch : std_logic; + +signal m_wb_cti_o : std_logic_vector(2 downto 0); +signal m_wb_bte_o : std_logic_vector(1 downto 0); + +signal control0 : std_logic_vector(35 downto 0); +signal data : std_logic_vector(63 downto 0); +signal trig0 : std_logic_vector(31 downto 0); + BEGIN -PCI_RSTn <= pci_rst_o when (pci_rst_oe_o = '1') else 'Z'; -PCI_INTAn <= pci_inta_o when (pci_inta_oe_o = '1') else 'Z'; -PCI_REQn <= pci_req_o when (pci_req_oe_o = '1') else 'Z'; -PCI_FRAMEn <= pci_frame_o when (pci_frame_oe_o = '1') else 'Z'; -PCI_IRDYn <= pci_irdy_o when (pci_irdy_oe_o = '1') else 'Z'; -PCI_DEVSELn <= pci_devsel_o when (pci_devsel_oe_o = '1') else 'Z'; -PCI_TRDYn <= pci_trdy_o when (pci_trdy_oe_o = '1') else 'Z'; -PCI_STOPn <= pci_stop_o when (pci_stop_oe_o = '1') else 'Z'; -PCI_PAR <= pci_par_o when (pci_par_oe_o = '1') else 'Z'; -PCI_PERRn <= pci_perr_o when (pci_perr_oe_o = '1') else 'Z'; -PCI_SERRn <= pci_serr_o when (pci_serr_oe_o = '1') else 'Z'; -MD_PAD_IO <= md_pad_o when (md_padoe_o = '1') else 'Z'; +IOBUF_PCI_RSTn: IOBUF +port map ( + IO => PCI_RSTn, + T => pci_rst_oe_o, + I => pci_rst_o, + O => pci_rst_i +); +IOBUF_PCI_INTAn: IOBUF +port map ( + IO => PCI_INTAn, + T => pci_inta_oe_o, + I => pci_inta_o, + O => pci_inta_i +); +OBUFT_PCI_REQn: OBUFT +port map ( + O => PCI_REQn, + T => pci_req_oe_o, + I => pci_req_o +); +IOBUF_PCI_FRAMEn: IOBUF +port map ( + IO => PCI_FRAMEn, + T => pci_frame_oe_o, + I => pci_frame_o, + O => pci_frame_i +); +IOBUF_PCI_IRDYn: IOBUF +port map ( + IO => PCI_IRDYn, + T => pci_irdy_oe_o, + I => pci_irdy_o, + O => pci_irdy_i +); +IOBUF_PCI_DEVSELn: IOBUF +port map ( + IO => PCI_DEVSELn, + T => pci_devsel_oe_o, + I => pci_devsel_o, + O => pci_devsel_i +); +IOBUF_PCI_TRDYn: IOBUF +port map ( + IO => PCI_TRDYn, + T => pci_trdy_oe_o, + I => pci_trdy_o, + O => pci_trdy_i +); +IOBUF_PCI_STOPn: IOBUF +port map ( + IO => PCI_STOPn, + T => pci_stop_oe_o, + I => pci_stop_o, + O => pci_stop_i +); +IOBUF_PCI_PAR: IOBUF +port map ( + IO => PCI_PAR, + T => pci_par_oe_o, + I => pci_par_o, + O => pci_par_i +); +IOBUF_PCI_PERRn: IOBUF +port map ( + IO => PCI_PERRn, + T => pci_perr_oe_o, + I => pci_perr_o, + O => pci_perr_i +); +IOBUF_PCI_SERRn: IOBUF +port map ( + IO => PCI_SERRn, + T => pci_serr_oe_o, + I => pci_serr_o, + O => pci_serr_i +); +IOBUF_MD_PAD_IO: IOBUF +port map ( + IO => MD_PAD_IO, + T => md_padoe_o, + I => md_pad_o, + O => md_pad_i +); BLA1: FOR i in 31 downto 0 generate -PCI_AD(i) <= pci_ad_o(i) when (pci_ad_oe_o(i) = '1') else 'Z'; +IOBUF_PCI_AD: IOBUF +port map ( + IO => PCI_AD(i), + T => pci_ad_oe_o(i), + I => pci_ad_o(i), + O => pci_ad_i(i) +); end generate; BLA2: FOR i in 3 downto 0 generate -PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z'; +IOBUF_PCI_CBEn: IOBUF +port map ( + IO => PCI_CBEn(i), + T => pci_cbe_oe_o(i), + I => pci_cbe_o(i), + O => pci_cbe_i(i) +); end generate; -wb_adr_i <= wbm_adr_o (11 downto 2); +wb_adr_i(11 downto 8) <= (others => '0'); +wb_adr_i(7 downto 2) <= wbm_adr_o (7 downto 2); + +wb_clk_i <= PCI_CLOCK; + +data(31 downto 0) <= wbm_adr_o; +data(39 downto 32) <= wbm_adr_o (7 downto 0); +data(40) <= md_pad_i; +data(41) <= md_pad_o; +data(42) <= md_padoe_o; +data(43) <= mdc_pad_o_watch; +data(44) <= pci_inta_o; +data(63 downto 45) <= (others => '0'); + +MDC_PAD_O <= mdc_pad_o_watch; + +trig0(31 downto 0) <= ( + 0 => wb_stb_i, + 1 => md_pad_i, + 2 => md_pad_o, + 3 => md_padoe_o, + others => '0' +); Inst_pci_bridge32: pci_bridge32 PORT MAP( wb_clk_i => wb_clk_i , @@ -240,8 +398,8 @@ Inst_pci_bridge32: pci_bridge32 PORT MAP( wbs_cyc_i => m_wb_cyc_o, wbs_stb_i => m_wb_stb_o, wbs_we_i => m_wb_we_o, - wbs_cti_i => (others => '0'), - wbs_bte_i => (others => '0'), + wbs_cti_i => m_wb_cti_o, + wbs_bte_i => m_wb_bte_o, wbs_ack_o => m_wb_ack_i, -- wbs_rty_o => , wbs_err_o => m_wb_err_i, @@ -258,16 +416,16 @@ Inst_pci_bridge32: pci_bridge32 PORT MAP( wbm_rty_i => '0', wbm_err_i => wb_err_o, pci_clk_i => PCI_CLOCK, - pci_rst_i => PCI_RSTn, + pci_rst_i => pci_rst_i, pci_rst_o => pci_rst_o , pci_rst_oe_o => pci_rst_oe_o, - pci_inta_i => PCI_INTAn, + pci_inta_i => pci_inta_i, pci_inta_o => pci_inta_o, pci_inta_oe_o => pci_inta_oe_o, pci_req_o => pci_req_o, pci_req_oe_o => pci_req_oe_o, pci_gnt_i => PCI_GNTn, - pci_frame_i => PCI_FRAMEn, + pci_frame_i => pci_frame_i, pci_frame_o => pci_frame_o, pci_frame_oe_o => pci_frame_oe_o, pci_irdy_oe_o => pci_irdy_oe_o, @@ -276,23 +434,23 @@ Inst_pci_bridge32: pci_bridge32 PORT MAP( pci_stop_oe_o => pci_stop_oe_o, pci_ad_oe_o => pci_ad_oe_o, pci_cbe_oe_o => pci_cbe_oe_o, - pci_irdy_i => PCI_IRDYn, + pci_irdy_i => pci_irdy_i, pci_irdy_o => pci_irdy_o, pci_idsel_i => PCI_IDSEL, - pci_devsel_i => PCI_DEVSELn, + pci_devsel_i => pci_devsel_i, pci_devsel_o => pci_devsel_o, - pci_trdy_i => PCI_TRDYn, + pci_trdy_i => pci_trdy_i, pci_trdy_o => pci_trdy_o, - pci_stop_i => PCI_STOPn, + pci_stop_i => pci_stop_i, pci_stop_o => pci_stop_o, - pci_ad_i => PCI_AD, + pci_ad_i => pci_ad_i, pci_ad_o => pci_ad_o, - pci_cbe_i => PCI_CBEn, + pci_cbe_i => pci_cbe_i, pci_cbe_o => pci_cbe_o, - pci_par_i => PCI_PAR, + pci_par_i => pci_par_i, pci_par_o => pci_par_o, pci_par_oe_o => pci_par_oe_o, - pci_perr_i => PCI_PERRn, + pci_perr_i => pci_perr_i, pci_perr_o => pci_perr_o, pci_perr_oe_o => pci_perr_oe_o, pci_serr_o => pci_serr_o, @@ -308,7 +466,7 @@ Inst_eth_top: eth_top PORT MAP( wb_sel_i => wb_sel_i , wb_we_i => wb_we_i , wb_cyc_i => wb_cyc_i , - wb_stb_i => wb_stb_i , + wb_stb_i => wb_stb_i, wb_ack_o => wb_ack_o , wb_err_o => wb_err_o , m_wb_adr_o => m_wb_adr_o, @@ -323,18 +481,42 @@ Inst_eth_top: eth_top PORT MAP( mtx_clk_pad_i => MTX_CLK_PAD_I, mtxd_pad_o => MTXD_PAD_O, mtxen_pad_o => MTXEN_PAD_O, - -- mtxerr_pad_o => , + mtxerr_pad_o => LED_2, mrx_clk_pad_i => MRX_CLK_PAD_I, mrxd_pad_i => MRXD_PAD_I, mrxdv_pad_i => MRXDV_PAD_I, mrxerr_pad_i => MRXERR_PAD_I, mcoll_pad_i => MCOLL_PAD_I, mcrs_pad_i => MCRS_PAD_I, - mdc_pad_o => MDC_PAD_O, - md_pad_i => MD_PAD_IO, + mdc_pad_o => mdc_pad_o_watch, + md_pad_i => md_pad_i, md_pad_o => md_pad_o, md_padoe_o => md_padoe_o, + m_wb_cti_o => m_wb_cti_o, + m_wb_bte_o => m_wb_bte_o, int_o => int_o ); +i_icon : icon +port map ( + control0 => control0 + ); + +i_ila : ila +port map ( + control => control0, + clk => PCI_CLOCK, + data => data, + trig0 => trig0 + ); + +eth_dcm : phydcm +port map ( + CLKIN_IN => PCI_CLOCK, + RST_IN => not pci_rst_i, + CLKFX_OUT => PHY_CLOCK, + CLK0_OUT => open, + LOCKED_OUT => open + ); + end architecture ethernet_arch;