X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/23944ea1558725bf7722ae42f0e5b52ed958eded..675f45d062971a8e9a17be7aa2f19b102d60c7b0:/ethernet/source/top.vhd

diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd
index d1a47da..1617eee 100644
--- a/ethernet/source/top.vhd
+++ b/ethernet/source/top.vhd
@@ -32,6 +32,8 @@ PORT(
         MD_PAD_IO : INOUT std_logic;
         MDC_PAD_O : OUT std_logic;
 
+	PHY_CLOCK : OUT std_logic;
+
 	LED_2 : OUT std_logic
 );
 end ethernet;
@@ -169,6 +171,14 @@ port (
 	);
 end component;
 
+component phydcm is
+port ( CLKIN_IN        : in    std_logic;
+       RST_IN          : in    std_logic;
+       CLKFX_OUT       : out   std_logic;
+       CLK0_OUT        : out   std_logic;
+       LOCKED_OUT      : out   std_logic);
+end component;
+
 signal pci_rst_o : std_logic;
 signal pci_rst_oe_o : std_logic;
 signal pci_inta_o : std_logic;
@@ -220,7 +230,6 @@ signal md_pad_o : std_logic;
 signal md_padoe_o : std_logic;
 signal int_o : std_logic;
 signal wbm_adr_o : std_logic_vector(31 downto 0);
-signal wb_stb_i_helper : std_logic_vector(31 downto 0);
 
 signal m_wb_cti_o : std_logic_vector(2 downto 0);
 signal m_wb_bte_o : std_logic_vector(1 downto 0);
@@ -253,10 +262,8 @@ BLA2: FOR i in 3 downto 0 generate
 PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z';
 end generate;
 
-wb_adr_i <= wbm_adr_o (11 downto 2);
-
-wb_stb_i_helper(32 downto 8) <= (others => '0');
-wb_stb_i_helper(7 downto 0) <= wbm_adr_o (7 downto 0);
+wb_adr_i(11 downto 8) <= (others => '0');
+wb_adr_i(7 downto 2)  <= wbm_adr_o (7 downto 2);
 
 wb_clk_i <= PCI_CLOCK;
 
@@ -350,7 +357,7 @@ Inst_eth_top: eth_top PORT MAP(
         wb_sel_i   => wb_sel_i  ,
         wb_we_i    => wb_we_i   ,
         wb_cyc_i   => wb_cyc_i  ,
-        wb_stb_i   => wb_stb_i_helper  ,
+        wb_stb_i   => wb_stb_i,
         wb_ack_o   => wb_ack_o  ,
         wb_err_o   => wb_err_o  ,
         m_wb_adr_o => m_wb_adr_o,
@@ -394,4 +401,13 @@ port map (
 	trig0 => trig0
 	);
 
+eth_dcm : phydcm
+port map (
+	CLKIN_IN => PCI_CLOCK,
+	RST_IN => not PCI_RSTn,
+	CLKFX_OUT => PHY_CLOCK,
+	CLK0_OUT => open,
+	LOCKED_OUT => open
+	);
+
 end architecture ethernet_arch;