X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/257c0fc1ab9ee166000bf5080191b0e62a507dc0..1afff8d481bb2d34c54b1c669b400bf706a9e7b6:/dhwk/source/top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index 215b980..dda8be1 100644
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -20,6 +20,10 @@ entity dhwk is
 --             SPC_RDY_IN : In    std_logic;
              TAST_RESn : In    std_logic;
              TAST_SETn : In    std_logic;
+             LED_2 : out    std_logic;
+             LED_3 : out    std_logic;
+             LED_4 : out    std_logic;
+             LED_5 : out    std_logic;
               PCI_AD : InOut std_logic_vector (31 downto 0);
              PCI_PAR : InOut std_logic;
              PCI_DEVSELn : Out   std_logic;
@@ -86,6 +90,10 @@ architecture SCHEMATIC of dhwk is
    signal SPC_RDY_IN : std_logic;
    signal SERIAL_OUT : std_logic;
    signal SPC_RDY_OUT : std_logic;
+   signal watch : std_logic;
+   signal control0       : std_logic_vector(35 downto 0);
+   signal data       : std_logic_vector(63 downto 0);
+   signal trig0      : std_logic_vector(7 downto 0);
 
    component MESS_1_TB
       Port ( DEVSELn : In    std_logic;
@@ -216,9 +224,54 @@ component fifo_generator_v3_2
         prog_full: OUT std_logic);
 end component;
 
+component icon
+port
+	(
+	 control0    :   out std_logic_vector(35 downto 0)
+	);
+end component;
+
+  component ila
+    port
+    (
+      control     : in    std_logic_vector(35 downto 0);
+      clk         : in    std_logic;
+      data        : in    std_logic_vector(63 downto 0);
+      trig0       : in    std_logic_vector(7 downto 0)
+    );
+  end component;
+
+
 begin
 	SERIAL_IN <= SERIAL_OUT;
 	SPC_RDY_IN <= SPC_RDY_OUT;
+	LED_2 <= TAST_RESn;
+	LED_3 <= TAST_SETn;
+	LED_4 <= '0';
+	LED_5 <= not watch;
+	PCI_INTAn <= watch;
+	trig0(7 downto 0) <= (others => '0');
+	data(31 downto 0) <= PCI_AD(31 downto 0);
+	data(32) <= watch;
+	
+	data(33) <= R_EFn;
+	data(34) <= R_HFn;
+	data(35) <= R_FFn;
+	data(36) <= R_FIFO_READn;
+	data(37) <= R_FIFO_RESETn;
+	data(38) <= R_FIFO_RTn;
+	data(39) <= R_FIFO_WRITEn;
+	data(40) <= S_EFn;
+	data(41) <= S_HFn;
+	data(42) <= S_FFn;
+	data(43) <= S_FIFO_READn;
+	data(44) <= S_FIFO_RESETn;
+	data(45) <= S_FIFO_RTn;
+	data(46) <= S_FIFO_WRITEn;
+	data(47) <= SERIAL_IN;
+	data(48) <= SPC_RDY_IN;
+	data(49) <= SERIAL_OUT;
+	data(50) <= SPC_RDY_OUT;
 
    I19 : MESS_1_TB
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
@@ -239,7 +292,7 @@ begin
                  READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
                  TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
                  TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
-                 INTAn=>INTAn, PCI_INTAn=>PCI_INTAn );
+                 INTAn=>INTAn, PCI_INTAn=>watch);
    I14 : FIFO_CONTROL
       Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
                  FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,
@@ -311,4 +364,19 @@ send_fifo : fifo_generator_v3_2
                         empty => S_EFn,
                         full => S_FFn,
                         prog_full => S_HFn);
+
+  i_icon : icon
+      port map
+          (
+	        control0    => control0
+	  );
+
+  i_ila : ila
+    port map
+    (
+      control   => control0,
+      clk       => PCI_CLOCK,
+      data      => data,
+      trig0     => trig0
+    );
 end SCHEMATIC;