X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/27f6f6203a7917361c6b1e482b03ab69c0e428a2..4d7b5fdda466a23785cf991038933df79abf4604:/ethernet/source/top.vhd

diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd
index 0541222..8c90690 100644
--- a/ethernet/source/top.vhd
+++ b/ethernet/source/top.vhd
@@ -30,7 +30,9 @@ PORT(
         MCOLL_PAD_I : IN std_logic;
         MCRS_PAD_I : IN std_logic;
         MD_PAD_IO : INOUT std_logic;
-        MDC_PAD_O : OUT std_logic
+        MDC_PAD_O : OUT std_logic;
+
+	LED_2 : OUT std_logic
 );
 end ethernet;
 
@@ -72,6 +74,8 @@ PORT(
         mdc_pad_o : OUT std_logic;
         md_pad_o : OUT std_logic;
         md_padoe_o : OUT std_logic;
+        m_wb_cti_o : OUT std_logic_vector(2 downto 0);
+        m_wb_bte_o : OUT std_logic_vector(1 downto 0);
         int_o : OUT std_logic
         );
 END COMPONENT;
@@ -202,6 +206,9 @@ signal md_padoe_o : std_logic;
 signal int_o : std_logic;
 signal wbm_adr_o : std_logic_vector(31 downto 0);
 
+signal m_wb_cti_o : std_logic_vector(2 downto 0);
+signal m_wb_bte_o : std_logic_vector(1 downto 0);
+
 BEGIN
 
 PCI_RSTn    <= pci_rst_o    when (pci_rst_oe_o = '1')     else 'Z';
@@ -240,8 +247,8 @@ Inst_pci_bridge32: pci_bridge32 PORT MAP(
         wbs_cyc_i => m_wb_cyc_o,
         wbs_stb_i => m_wb_stb_o,
         wbs_we_i => m_wb_we_o,
-        wbs_cti_i => (others => '0'),
-        wbs_bte_i => (others => '0'),
+        wbs_cti_i => m_wb_cti_o,
+        wbs_bte_i => m_wb_bte_o,
         wbs_ack_o => m_wb_ack_i,
         -- wbs_rty_o => ,
         wbs_err_o => m_wb_err_i,
@@ -323,7 +330,7 @@ Inst_eth_top: eth_top PORT MAP(
         mtx_clk_pad_i => MTX_CLK_PAD_I,
         mtxd_pad_o => MTXD_PAD_O,
         mtxen_pad_o => MTXEN_PAD_O,
-        -- mtxerr_pad_o => ,
+        mtxerr_pad_o => LED_2,
         mrx_clk_pad_i => MRX_CLK_PAD_I,
         mrxd_pad_i => MRXD_PAD_I,
         mrxdv_pad_i => MRXDV_PAD_I,
@@ -334,6 +341,8 @@ Inst_eth_top: eth_top PORT MAP(
         md_pad_i => MD_PAD_IO,
         md_pad_o => md_pad_o,
         md_padoe_o => md_padoe_o,
+        m_wb_cti_o => m_wb_cti_o,
+        m_wb_bte_o => m_wb_bte_o, 
         int_o => int_o
 );