X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/2825d08e6e5a5c0ba429f454065da84d6623cf9f..078adaa6dde598b83d746458dd7140f567223e6a:/dhwk/source/top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index 3036632..bf927d8 100644
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -16,10 +16,14 @@ entity dhwk is
              PCI_IDSEL : In    std_logic;
              PCI_IRDYn : In    std_logic;
              PCI_RSTn : In    std_logic;
-             SERIAL_IN : In    std_logic;
-             SPC_RDY_IN : In    std_logic;
+--             SERIAL_IN : In    std_logic;
+--             SPC_RDY_IN : In    std_logic;
              TAST_RESn : In    std_logic;
              TAST_SETn : In    std_logic;
+             LED_2 : out    std_logic;
+             LED_3 : out    std_logic;
+             LED_4 : out    std_logic;
+             LED_5 : out    std_logic;
               PCI_AD : InOut std_logic_vector (31 downto 0);
              PCI_PAR : InOut std_logic;
              PCI_DEVSELn : Out   std_logic;
@@ -28,8 +32,8 @@ entity dhwk is
              PCI_SERRn : Out   std_logic;
              PCI_STOPn : Out   std_logic;
              PCI_TRDYn : Out   std_logic;
-             SERIAL_OUT : Out   std_logic;
-             SPC_RDY_OUT : Out   std_logic;
+--             SERIAL_OUT : Out   std_logic;
+--             SPC_RDY_OUT : Out   std_logic;
              TB_IDSEL : Out   std_logic;
              TB_nDEVSEL : Out   std_logic;
              TB_nINTA : Out   std_logic );
@@ -82,6 +86,14 @@ architecture SCHEMATIC of dhwk is
    signal S_FIFO_RESETn : std_logic;
    signal S_FIFO_RTn : std_logic;
    signal S_FIFO_WRITEn : std_logic;
+   signal SERIAL_IN : std_logic;
+   signal SPC_RDY_IN : std_logic;
+   signal SERIAL_OUT : std_logic;
+   signal SPC_RDY_OUT : std_logic;
+   signal watch : std_logic;
+   signal control0       : std_logic_vector(35 downto 0);
+   signal data       : std_logic_vector(95 downto 0);
+   signal trig0      : std_logic_vector(31 downto 0);
 
    component MESS_1_TB
       Port ( DEVSELn : In    std_logic;
@@ -197,7 +209,7 @@ architecture SCHEMATIC of dhwk is
              WRITE_XX7_6 : Out   std_logic );
    end component;
 
-component fifo_generator_v3_2
+component dhwk_fifo
         port (
         clk: IN std_logic;
         din: IN std_logic_VECTOR(7 downto 0);
@@ -212,7 +224,77 @@ component fifo_generator_v3_2
         prog_full: OUT std_logic);
 end component;
 
+component icon
+port
+	(
+	 control0    :   out std_logic_vector(35 downto 0)
+	);
+end component;
+
+  component ila
+    port
+    (
+      control     : in    std_logic_vector(35 downto 0);
+      clk         : in    std_logic;
+      data        : in    std_logic_vector(95 downto 0);
+      trig0       : in    std_logic_vector(31 downto 0)
+    );
+  end component;
+
+
 begin
+	SERIAL_IN <= SERIAL_OUT;
+	SPC_RDY_IN <= SPC_RDY_OUT;
+	LED_2 <= TAST_RESn;
+	LED_3 <= TAST_SETn;
+	LED_4 <= '0';
+	LED_5 <= not watch;
+	PCI_INTAn <= watch;
+	trig0(31 downto 0) <= (
+		0 => watch,
+		1 => R_FIFO_READn,
+		2 => R_FIFO_WRITEn,
+		3 => S_FIFO_READn,
+		4 => S_FIFO_WRITEn, 
+		16 => PCI_AD(0),
+		17 => PCI_AD(1),
+		18 => PCI_AD(2),
+		19 => PCI_AD(3),
+		20 => PCI_AD(4),
+		21 => PCI_AD(5),
+		22 => PCI_AD(6),
+		23 => PCI_AD(7),
+		27 => PCI_FRAMEn,
+		28 => PCI_CBEn(0),
+		29 => PCI_CBEn(1),
+		30 => PCI_CBEn(2),
+		31 => PCI_CBEn(3),
+		others => '0');
+
+	data(0) <= watch;
+	data(1) <= R_EFn;
+	data(2) <= R_HFn;
+	data(3) <= R_FFn;
+	data(4) <= R_FIFO_READn;
+	data(5) <= R_FIFO_RESETn;
+	data(6) <= R_FIFO_RTn;
+	data(7) <= R_FIFO_WRITEn;
+	data(8) <= S_EFn;
+	data(9) <= S_HFn;
+	data(10) <= S_FFn;
+	data(11) <= S_FIFO_READn;
+	data(12) <= S_FIFO_RESETn;
+	data(13) <= S_FIFO_RTn;
+	data(14) <= S_FIFO_WRITEn;
+	data(15) <= SERIAL_IN;
+	data(16) <= SPC_RDY_IN;
+	data(17) <= SERIAL_OUT;
+	data(18) <= SPC_RDY_OUT;
+	data(26 downto 19) <= S_FIFO_Q_OUT;
+	data(34 downto 27) <= R_FIFO_Q_OUT;
+	data(66 downto 35) <= PCI_AD(31 downto 0);
+	data(70 downto 67) <= PCI_CBEn(3 downto 0);
+	data(71) <= PCI_FRAMEn;
 
    I19 : MESS_1_TB
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
@@ -233,7 +315,7 @@ begin
                  READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
                  TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
                  TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
-                 INTAn=>INTAn, PCI_INTAn=>PCI_INTAn );
+                 INTAn=>INTAn, PCI_INTAn=>watch);
    I14 : FIFO_CONTROL
       Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
                  FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,
@@ -282,7 +364,7 @@ begin
                  WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
                  WRITE_XX7_6=>WRITE_XX7_6 );
 
-receive_fifo : fifo_generator_v3_2
+receive_fifo : dhwk_fifo
                 port map (
                         clk => PCI_CLOCK,
                         din => R_FIFO_D_IN,
@@ -294,7 +376,7 @@ receive_fifo : fifo_generator_v3_2
                         full => R_FFn,
                         prog_full => R_HFn);
 
-send_fifo : fifo_generator_v3_2
+send_fifo : dhwk_fifo
                 port map (
                         clk => PCI_CLOCK,
                         din => S_FIFO_D_IN,
@@ -305,4 +387,19 @@ send_fifo : fifo_generator_v3_2
                         empty => S_EFn,
                         full => S_FFn,
                         prog_full => S_HFn);
+
+  i_icon : icon
+      port map
+          (
+	        control0    => control0
+	  );
+
+  i_ila : ila
+    port map
+    (
+      control   => control0,
+      clk       => PCI_CLOCK,
+      data      => data,
+      trig0     => trig0
+    );
 end SCHEMATIC;