X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/2d8e1276d2533e26fcbc241b34dcc0af17eed492..2245a9fc38ae7959867a57992da382b22117b8a4:/dhwk_old/source/top_dhwk.vhd?ds=sidebyside

diff --git a/dhwk_old/source/top_dhwk.vhd b/dhwk_old/source/top_dhwk.vhd
index accd1a3..13de352 100644
--- a/dhwk_old/source/top_dhwk.vhd
+++ b/dhwk_old/source/top_dhwk.vhd
@@ -109,7 +109,7 @@ port (
 );
 end component;
 
-component wb_7seg_new
+component wb_fifo
 port (
 	clk_i		: in std_logic;
 	nrst_i		: in std_logic;
@@ -125,8 +125,11 @@ port (
 	wb_err_o	: out std_logic;
 	wb_int_o	: out std_logic;
 	
-	DISP_SEL	: inout std_logic_vector(3 downto 0);
-	DISP_LED	: out std_logic_vector(6 downto 0)
+	fifo_data_i	: in std_logic_vector(7 downto 0);
+	fifo_data_o     : out std_logic_vector(7 downto 0);
+
+	fifo_we_o	: out std_logic;
+	fifo_re_o	: out std_logic
 );
 end component;
 
@@ -141,6 +144,12 @@ signal	wb_ack :		std_logic;
 signal	wb_err :		std_logic;
 signal	wb_int :		std_logic;
 
+signal fifo_din		: std_logic_vector(7 downto 0);
+signal fifo_dout	: std_logic_vector(7 downto 0);
+signal fifo_we		: std_logic;
+signal fifo_re		: std_logic;
+
+
 
 begin
 
@@ -172,7 +181,50 @@ port map(
 		wb_int_i =>		wb_int
 --		debug_init =>	LED3,
 --		debug_access =>	LED2
-		);
+);
+
+my_generic_fifo: component generic_fifo_sc_a
+port map(
+	clk		=> PCI_CLK,
+	rst		=> PCI_nRES,
+	clr		=> '0',
+	din		=> fifo_din,
+	we		=> fifo_we,
+	dout		=> fifo_dout,
+	re		=> fifo_re
+--	full		=> ,
+--	full_r		=> ,
+--	empty		=> ,
+--	empty_r		=> ,
+--	full_n		=> ,
+--	full_n_r	=> ,
+--	empty_n		=> ,
+--	empty_n_r	=> ,
+--	level		=> ,
+);
+
+my_fifo: component wb_fifo
+port map(
+	clk_i		 => PCI_CLK,
+	nrst_i		 => PCI_nRES,
+
+	wb_adr_i	 => wb_adr,
+	wb_dat_o	 => wb_dat_out,
+	wb_dat_i	 => wb_dat_in,
+	wb_sel_i	 => wb_sel,
+	wb_we_i		 => wb_we,
+	wb_stb_i	 => wb_stb,
+	wb_cyc_i	 => wb_cyc,
+	wb_ack_o	 => wb_ack,
+	wb_err_o	 => wb_err,
+	wb_int_o	 => wb_int,
+
+	fifo_data_i	 => fifo_dout,
+	fifo_data_o      => fifo_din,
+
+	fifo_we_o	 => fifo_we,
+	fifo_re_o	 => fifo_re
+);
 
 my_heartbeat: component heartbeat
 port map(