X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/30273618403fd6512926c89f999f97b4722e1709..70f633de02777501eba552b2a46df48f37dab136:/dhwk/source/pci/top.vhd

diff --git a/dhwk/source/pci/top.vhd b/dhwk/source/pci/top.vhd
index e16f512..5c4851a 100644
--- a/dhwk/source/pci/top.vhd
+++ b/dhwk/source/pci/top.vhd
@@ -90,6 +90,7 @@ architecture SCHEMATIC of dhwk is
         signal SPC_RDY_IN : std_logic;
         signal SERIAL_OUT : std_logic;
         signal SPC_RDY_OUT : std_logic;
+        signal led_PCI_INTA : std_logic;
         signal watch_PCI_INTAn : std_logic;
         signal watch_PCI_TRDYn : std_logic;
         signal watch_PCI_STOPn : std_logic;
@@ -97,8 +98,11 @@ architecture SCHEMATIC of dhwk is
         signal watch_PCI_PERRn : std_logic;
         signal watch_PCI_REQn : std_logic;
         signal control0 : std_logic_vector(35 downto 0);
+        signal control1 : std_logic_vector(35 downto 0);
         signal data : std_logic_vector(95 downto 0);
         signal trig0 : std_logic_vector(31 downto 0);
+	signal vio_sync_out : std_logic_vector(0 downto 0);
+	signal vio_async_in : std_logic_vector(3 downto 0);
 
         component MESS_1_TB
                 Port ( DEVSELn : In std_logic;
@@ -232,7 +236,8 @@ architecture SCHEMATIC of dhwk is
         component icon
                 port
                 (
-                        control0 : out std_logic_vector(35 downto 0)
+                        control0 : out std_logic_vector(35 downto 0);
+                        control1 : out std_logic_vector(35 downto 0)
                 );
         end component;
 
@@ -246,16 +251,41 @@ architecture SCHEMATIC of dhwk is
                 );
         end component;
 
+	component vio
+		port
+		(
+			control : in std_logic_vector(35 downto 0);
+			clk : in std_logic;
+			async_in : in std_logic_vector(3 downto 0);
+			sync_out : out std_logic_vector(0 downto 0)
+		);
+	end component;
+
 
 begin
+	process(PCI_CLOCK)
+	begin
+		if rising_edge(PCI_CLOCK) then
+			led_PCI_INTA <= not (watch_PCI_INTAn and (not vio_sync_out(0)));
+		end if;
+	end process;
+
         watch_PCI_REQn <= '1';
         SERIAL_IN <= SERIAL_OUT;
         SPC_RDY_IN <= SPC_RDY_OUT;
         LED_2 <= not PCI_RSTn;
-        LED_3 <= PCI_IDSEL;
+        LED_3 <= not PCI_IDSEL;
         LED_4 <= not PCI_FRAMEn;
-        LED_5 <= not watch_PCI_INTAn;
-        PCI_INTAn <= watch_PCI_INTAn;
+	LED_5 <= led_PCI_INTA;
+        PCI_INTAn <= (watch_PCI_INTAn and (not vio_sync_out(0)));
+
+	vio_async_in(3 downto 0) <= (
+	0 => not PCI_RSTn,
+	1 => not PCI_IDSEL,
+	2 => not PCI_FRAMEn,
+	3 => led_PCI_INTA
+	);
+
         trig0(31 downto 0) <= (
         0 => watch_PCI_INTAn,
         1 => R_FIFO_READn,
@@ -263,6 +293,7 @@ begin
         3 => S_FIFO_READn,
         4 => S_FIFO_WRITEn,
         5 => PCI_RSTn,
+	6 => PCI_IDSEL,
         16 => PCI_AD(0),
         17 => PCI_AD(1),
         18 => PCI_AD(2),
@@ -411,7 +442,8 @@ begin
         i_icon : icon
         port map
         (
-                control0 => control0
+                control0 => control0,
+                control1 => control1
         );
 
         i_ila : ila
@@ -422,4 +454,13 @@ begin
                 data => data,
                 trig0 => trig0
         );
+
+	i_vio : vio
+	port map
+	(
+		control => control1,
+		clk => PCI_CLOCK,
+		async_in => vio_async_in,
+		sync_out => vio_sync_out
+	);
 end SCHEMATIC;