X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/36a53ce255c40f7051820ffbaaac1dd646a83bfb..377c02420489dd18db3ce053a075d7eca4ae799b:/dhwk/source/FLAG_BUS.vhd

diff --git a/dhwk/source/FLAG_BUS.vhd b/dhwk/source/FLAG_BUS.vhd
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+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: FLAG_BUS.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity FLAG_BUS is
+	port
+	(
+	PCI_CLOCK	:in		std_logic;
+	KONS_1		:in		std_logic;
+	FLAG_IN_0	:in		std_logic;
+	R_EFn			:in		std_logic;
+	R_HFn			:in		std_logic;
+	R_FFn			:in		std_logic;
+	FLAG_IN_4	:in		std_logic;
+	S_EFn			:in		std_logic;
+	S_HFn			:in		std_logic;
+	S_FFn			:in		std_logic;
+	HOLD			:in		std_logic;
+	SYNC_FLAG	:out	std_logic_vector (7 downto 0)
+	);	
+end entity FLAG_BUS;
+
+architecture FLAG_BUS_DESIGN of FLAG_BUS is
+
+
+signal	FF1_S_EFn	:std_logic;	
+signal	FF1_S_HFn	:std_logic;
+signal	FF1_S_FFn	:std_logic;
+signal	FF1_R_EFn	:std_logic;
+signal	FF1_R_HFn	:std_logic;
+signal	FF1_R_FFn	:std_logic;
+
+signal	FF2_S_EFn	:std_logic;	
+signal	FF2_S_HFn	:std_logic;
+signal	FF2_S_FFn	:std_logic;
+signal	FF2_R_EFn	:std_logic;
+signal	FF2_R_HFn	:std_logic;
+signal	FF2_R_FFn	:std_logic;
+
+begin
+
+
+	process	(PCI_CLOCK) 
+	begin 
+		if	(PCI_CLOCK'event	and	PCI_CLOCK	=	'1')	then 
+
+		FF1_S_EFn	<=	S_EFn;
+		FF1_S_HFn	<=	S_HFn;
+		FF1_S_FFn	<=	S_FFn;
+		FF1_R_EFn	<=	R_EFn;
+		FF1_R_HFn	<=	R_HFn;
+		FF1_R_FFn	<=	R_FFn;
+
+		end if;
+	end process; 	
+
+
+	process	(PCI_CLOCK) 
+	begin 
+		if	(PCI_CLOCK'event	and	PCI_CLOCK	=	'1')	then  
+
+			if			HOLD	=	'0'	then
+
+					FF2_S_EFn	<=	FF1_S_EFn;	
+					FF2_S_HFn	<=	FF1_S_HFn;
+					FF2_S_FFn	<=	FF1_S_FFn;
+					FF2_R_EFn	<=	FF1_R_EFn;
+					FF2_R_HFn	<=	FF1_R_HFn;
+					FF2_R_FFn	<=	FF1_R_FFn;
+
+				elsif	HOLD	=	'1'	then
+
+					FF2_S_EFn	<=	FF2_S_EFn;	
+					FF2_S_HFn	<=	FF2_S_HFn;
+					FF2_S_FFn	<=	FF2_S_FFn;
+					FF2_R_EFn	<=	FF2_R_EFn;
+					FF2_R_HFn	<=	FF2_R_HFn;
+					FF2_R_FFn	<=	FF2_R_FFn;
+
+			end if;
+		end if;
+	end process; 	
+
+	SYNC_FLAG(0)	<=	FLAG_IN_0;		
+	SYNC_FLAG(1)	<=	FF2_R_EFn;	
+	SYNC_FLAG(2)	<=	FF2_R_HFn;
+	SYNC_FLAG(3)	<=	FF2_R_FFn;
+	SYNC_FLAG(4)	<=	FLAG_IN_4;		
+	SYNC_FLAG(5)	<=	FF2_S_EFn;	
+	SYNC_FLAG(6)	<=	FF2_S_HFn;
+	SYNC_FLAG(7)	<=	FF2_S_FFn;
+
+end architecture FLAG_BUS_DESIGN;
+