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+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: REG.VHD
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity REG is
+	port
+	(
+	CLOCK		:in		std_logic; 
+	RESET		:in		std_logic; 
+	WRITE		:in		std_logic;   
+	REG_IN	:in		std_logic_vector(7 downto 0);
+	REG_OUT	:out	std_logic_vector(7 downto 0) 
+	);
+end entity REG ;
+
+architecture REG_DESIGN of REG is
+
+	signal SIG_REG	:std_logic_vector (7 downto 0);
+
+begin
+
+	process (CLOCK) 
+	begin
+		if (CLOCK'event and CLOCK = '1') then
+			if			RESET	=	'1'	then	SIG_REG	<= X"00";
+				elsif	WRITE	=	'1'	then	SIG_REG	<= REG_IN;
+ 				else										SIG_REG	<= SIG_REG;
+  		end if;
+		end if;
+	end process;
+
+	REG_OUT <= SIG_REG;
+
+end architecture REG_DESIGN;