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+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_8.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity VERG_8 is
+	port
+	(
+	GLEICH			:in		std_logic_vector(7 downto 0);
+	GLEICH_OUT	:out	std_logic
+	);
+
+end entity VERG_8 ;
+
+architecture VERG_8_DESIGN of VERG_8 is
+ 
+
+begin
+
+--	GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte
+
+--	GLEICH_OUT	<=	'1'	when	GLEICH(7 downto 0)	=	"11111111"	else	'0';    
+		GLEICH_OUT	<=	'1'	when	GLEICH(7 downto 1)	=	"1111111"		else	'0'; 
+ 
+end architecture VERG_8_DESIGN ;