X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/36a53ce255c40f7051820ffbaaac1dd646a83bfb..528d015aa19100f9f97b3469ab7d2aafa43b425e:/heartbeat/source/top_raggedstone.vhd

diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd
index c798294..01dc26b 100644
--- a/heartbeat/source/top_raggedstone.vhd
+++ b/heartbeat/source/top_raggedstone.vhd
@@ -44,6 +44,7 @@ port (
     -- General 
     PCI_CLK     : in std_logic;
     PCI_nRES    : in std_logic;
+    PCI_nREQ    : out std_logic;
     
     -- PCI target 32bits
     PCI_AD      : inout std_logic_vector(31 downto 0);
@@ -63,11 +64,11 @@ port (
 	LED3	: out std_logic;
 	LED2	: out std_logic;
 	LED4		: out std_logic;
-	LED5		: out std_logic;
-	IDE1	: out std_logic;
-	IDE2	: out std_logic;
-	IDE3	: out std_logic;
-	IDE4	: out std_logic
+	LED5		: out std_logic
+--	IDE1	: out std_logic;
+--	IDE2	: out std_logic;
+--	IDE3	: out std_logic;
+--	IDE4	: out std_logic
 
 );
 end raggedstone;
@@ -161,6 +162,8 @@ end component;
 
 begin
 
+	PCI_nREQ <= '1';
+
 --+-----------------------------------------+
 --|  PCI Target 							|
 --+-----------------------------------------+
@@ -206,11 +209,11 @@ port map(
 	led2_o => LED2,
 	led3_o => LED3,
 	led4_o => LED4,
-	led5_o => LED5,
-	led6_o => IDE1,
-	led7_o => IDE2,
-	led8_o => IDE3,
-	led9_o => IDE4
+	led5_o => LED5
+--	led6_o => IDE1,
+--	led7_o => IDE2,
+--	led8_o => IDE3,
+--	led9_o => IDE4
 );
 
 end raggedstone_arch;