X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/377c02420489dd18db3ce053a075d7eca4ae799b..0b6ed0d89260ade25dc0c2dc9fb8aa154fabd6a1:/dhwk/source/REG.vhd

diff --git a/dhwk/source/REG.vhd b/dhwk/source/REG.vhd
index 0c91d25..7201b3a 100644
--- a/dhwk/source/REG.vhd
+++ b/dhwk/source/REG.vhd
@@ -1,38 +1,43 @@
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: REG.VHD
-
-library ieee ;
-use ieee.std_logic_1164.all ;
-
-entity REG is
-	port
-	(
-	CLOCK		:in		std_logic; 
-	RESET		:in		std_logic; 
-	WRITE		:in		std_logic;   
-	REG_IN	:in		std_logic_vector(7 downto 0);
-	REG_OUT	:out	std_logic_vector(7 downto 0) 
-	);
-end entity REG ;
-
-architecture REG_DESIGN of REG is
-
-	signal SIG_REG	:std_logic_vector (7 downto 0);
-
-begin
-
-	process (CLOCK) 
-	begin
-		if (CLOCK'event and CLOCK = '1') then
-			if			RESET	=	'1'	then	SIG_REG	<= X"00";
-				elsif	WRITE	=	'1'	then	SIG_REG	<= REG_IN;
- 				else										SIG_REG	<= SIG_REG;
-  		end if;
-		end if;
-	end process;
-
-	REG_OUT <= SIG_REG;
-
-end architecture REG_DESIGN;
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: REG.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity REG is
+        port
+        (
+                CLOCK :in std_logic;
+                RESET :in std_logic;
+                WRITE :in std_logic;
+                REG_IN :in std_logic_vector(7 downto 0);
+                REG_OUT :out std_logic_vector(7 downto 0)
+        );
+end entity REG;
+
+architecture REG_DESIGN of REG is
+
+        signal SIG_REG :std_logic_vector (7 downto 0);
+
+begin
+
+        process (CLOCK)
+        begin
+                if (CLOCK'event and CLOCK = '1') then
+                        if RESET = '1' then
+                                SIG_REG <= X"00";
+
+                        elsif WRITE = '1' then
+                                SIG_REG <= REG_IN;
+
+                        else
+                                SIG_REG <= SIG_REG;
+                        end if;
+                end if;
+        end process;
+
+        REG_OUT <= SIG_REG;
+
+end architecture REG_DESIGN;