X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/377c02420489dd18db3ce053a075d7eca4ae799b..0b6ed0d89260ade25dc0c2dc9fb8aa154fabd6a1:/dhwk/source/Verg_2.vhd

diff --git a/dhwk/source/Verg_2.vhd b/dhwk/source/Verg_2.vhd
index 39d51ac..bbea0ea 100644
--- a/dhwk/source/Verg_2.vhd
+++ b/dhwk/source/Verg_2.vhd
@@ -1,31 +1,33 @@
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: VERG_2.VHD
-
-library ieee ;
-use ieee.std_logic_1164.all ;
-
-entity	VERG_2	is
-	port
-	(
- 	IN_A		:in		std_logic_vector(1 downto 0);
- 	IN_B		:in		std_logic_vector(1 downto 0);
-	GLEICH	:out	std_logic
-	);
-end entity VERG_2 ;
-
-architecture VERG_2_DESIGN of VERG_2 is
-
-begin
-
-	process (IN_A,IN_B) 
-	begin 
-
-		if			IN_A	=	IN_B	then	GLEICH	<=	'1';
-			else											GLEICH	<=	'0';   
-		end if;
-
-	end process;
-
-end architecture VERG_2_DESIGN ;
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_2.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity VERG_2 is
+        port
+        (
+                IN_A :in std_logic_vector(1 downto 0);
+                IN_B :in std_logic_vector(1 downto 0);
+                GLEICH :out std_logic
+        );
+end entity VERG_2;
+
+architecture VERG_2_DESIGN of VERG_2 is
+
+begin
+
+        process (IN_A,IN_B)
+        begin
+
+        if IN_A = IN_B then
+                GLEICH <= '1';
+        else
+                GLEICH <= '0';
+        end if;
+
+end process;
+
+end architecture VERG_2_DESIGN;