X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/377c02420489dd18db3ce053a075d7eca4ae799b..0b6ed0d89260ade25dc0c2dc9fb8aa154fabd6a1:/dhwk/source/connecting_fsm.vhd

diff --git a/dhwk/source/connecting_fsm.vhd b/dhwk/source/connecting_fsm.vhd
index ab8f54f..eb444ea 100644
--- a/dhwk/source/connecting_fsm.vhd
+++ b/dhwk/source/connecting_fsm.vhd
@@ -1,136 +1,145 @@
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: CONNECTING_FSM.VHD
-
-library ieee ;
-use ieee.std_logic_1164.all ;
-
-entity CONNECTING_FSM is
-	port
-	(
-	PCI_CLOCK				:in		std_logic; 
-	RESET						:in		std_logic; 
-	PSC_ENABLE			:in		std_logic;
-	SYNC_S_FIFO_EFn	:in		std_logic;
-	SPC_ENABLE			:in		std_logic;
-	SYNC_R_FIFO_FFn	:in		std_logic;
- 	S_FIFO_Q_OUT		:in		std_logic_vector(7 downto 0);
-	S_FIFO_READn		:out	std_logic;
-	R_FIFO_WRITEn		:out	std_logic;
-	R_FIFO_D_IN			:out	std_logic_vector(7 downto 0) 
-	);
-end entity CONNECTING_FSM;
-
-architecture CONNECTING_FSM_DESIGN of CONNECTING_FSM is
-
-	signal REG						:std_logic_vector(7 downto 0);
-	signal HELP_0,HELP_1	:std_logic;
-	signal SIG_LOAD				:std_logic;
-
-
---**********************************************************
---***         CONNECTING FSM CODIERUNG                   ***
---**********************************************************
---
---
---                                                 ---------- HELP_0
---                                               	 |--------- HELP_1   
---                                              	 ||-------- LOAD   
---                                             	   |||------- WRITE   
---																							   ||||------ READ   
---																								 |||||     
-	constant	S0	:std_logic_vector(4 downto 0)	:=	"00011";--
-	constant	S1	:std_logic_vector(4 downto 0)	:=	"01010";--READ
-	constant	S2	:std_logic_vector(4 downto 0) :=	"10010";--READ
-	constant	S3	:std_logic_vector(4 downto 0) :=	"11110";--READ,LOAD
-	constant	S4	:std_logic_vector(4 downto 0) :=	"11011";--
-	constant	S5	:std_logic_vector(4 downto 0) :=	"01001";--WRITE
-	constant	S6	:std_logic_vector(4 downto 0) :=	"10001";--WRITE
-	constant	S7	:std_logic_vector(4 downto 0) :=	"11001";--WRITE
-
-	signal STATES	:std_logic_vector(4 downto 0);
-
---************************************************************
---***             FSM SPEICHER-AUTOMAT                     ***
---************************************************************
-
-	attribute	syn_state_machine	:	boolean;
-	attribute	syn_state_machine	of	STATES	:	signal	is	false;
-
---************************************************************
---***             		REGISTER BESCHREIBUNG	               ***
---************************************************************
-
-begin
-
-	process (PCI_CLOCK) 
-	begin
-		if	(PCI_CLOCK'event	and	PCI_CLOCK	=	'1')	then
-			if			SIG_LOAD	=	'1'	then	REG	<=	S_FIFO_Q_OUT;
-				elsif	SIG_LOAD	=	'0'	then	REG	<=	REG;   
-			end if;
-		end if;
-	end process;
-
---************************************************************
---***             		FSM BESCHREIBUNG		                 ***
---************************************************************
-
-	process (PCI_CLOCK)
-	begin  
-		if	(PCI_CLOCK'event	and	PCI_CLOCK	=	'1')	then
-  
-			if	RESET	=	'1'	then	STATES <= S0;
-				else
-  
-					case	STATES is
-
-					when	S0	=> 
-						if	PSC_ENABLE			= '1'	and
-								SPC_ENABLE			=	'1'	and
-								SYNC_S_FIFO_EFn	=	'1'	then
-
-												STATES	<=	S1;
-							else  
-												STATES	<=	S0;
-						end if;
-
-					when	S1	=>	STATES	<=	S2;
-					when	S2	=>	STATES	<=	S3;
-					when	S3	=>	STATES	<=	S4;
-
-					when	S4	=> 
-						if	SYNC_R_FIFO_FFn	=	'1'	then
-
-												STATES	<=	S5;
-						else  
-    		                STATES	<=	S4;
-						end if;
-
-					when	S5	=>	STATES	<=	S6;
-					when	S6	=>	STATES	<=	S7;
-					when	S7	=>	STATES	<=	S0;
-
-					when others => 
-
-												STATES	<=	S0; 
-
-				end case;		-- STATES    
-			end if;				-- RESET 
-		end if;					-- PCI_CLOCK   
-	end process;			-- PROCESS
-
---************************************************************
---***      	ZUWEISUNG 	signal/out	<= 	STATES             ***
---************************************************************
-
-	HELP_0				<=	STATES(4);  
-	HELP_1				<=	STATES(3);
-	SIG_LOAD			<=	STATES(2);
-	R_FIFO_WRITEn	<=	STATES(1);
-	S_FIFO_READn	<=	STATES(0);
-
-	R_FIFO_D_IN		<=	REG;
-
-end architecture CONNECTING_FSM_DESIGN;
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONNECTING_FSM.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity CONNECTING_FSM is
+        port
+        (
+                PCI_CLOCK :in std_logic;
+                RESET :in std_logic;
+                PSC_ENABLE :in std_logic;
+                SYNC_S_FIFO_EFn :in std_logic;
+                SPC_ENABLE :in std_logic;
+                SYNC_R_FIFO_FFn :in std_logic;
+                S_FIFO_Q_OUT :in std_logic_vector(7 downto 0);
+                S_FIFO_READn :out std_logic;
+                R_FIFO_WRITEn :out std_logic;
+                R_FIFO_D_IN :out std_logic_vector(7 downto 0)
+        );
+end entity CONNECTING_FSM;
+
+architecture CONNECTING_FSM_DESIGN of CONNECTING_FSM is
+
+        signal REG :std_logic_vector(7 downto 0);
+        signal HELP_0,HELP_1 :std_logic;
+        signal SIG_LOAD :std_logic;
+
+
+ --**********************************************************
+ --*** CONNECTING FSM CODIERUNG ***
+ --**********************************************************
+ --
+ --
+ -- ---------- HELP_0
+ -- |--------- HELP_1
+ -- ||-------- LOAD
+ -- |||------- WRITE
+ -- ||||------ READ
+ -- |||||
+        constant S0 :std_logic_vector(4 downto 0) := "00011";--
+        constant S1 :std_logic_vector(4 downto 0) := "01010";--READ
+        constant S2 :std_logic_vector(4 downto 0) := "10010";--READ
+        constant S3 :std_logic_vector(4 downto 0) := "11110";--READ,LOAD
+        constant S4 :std_logic_vector(4 downto 0) := "11011";--
+        constant S5 :std_logic_vector(4 downto 0) := "01001";--WRITE
+        constant S6 :std_logic_vector(4 downto 0) := "10001";--WRITE
+        constant S7 :std_logic_vector(4 downto 0) := "11001";--WRITE
+
+        signal STATES :std_logic_vector(4 downto 0);
+
+ --************************************************************
+ --*** FSM SPEICHER-AUTOMAT ***
+ --************************************************************
+
+        attribute syn_state_machine : boolean;
+        attribute syn_state_machine of STATES : signal is false;
+
+--************************************************************
+--*** REGISTER BESCHREIBUNG ***
+--************************************************************
+
+begin
+
+        process (PCI_CLOCK)
+        begin
+                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                        if SIG_LOAD = '1' then
+                                REG <= S_FIFO_Q_OUT;
+
+                        elsif SIG_LOAD = '0' then
+                                REG <= REG;
+                        end if;
+                end if;
+ end process;
+
+ --************************************************************
+ --*** FSM BESCHREIBUNG ***
+ --************************************************************
+
+process (PCI_CLOCK)
+begin
+        if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+
+                if RESET = '1' then
+                        STATES <= S0;
+                else
+
+                       case STATES is
+
+                       when S0 =>
+                               if PSC_ENABLE = '1' and SPC_ENABLE = '1' and SYNC_S_FIFO_EFn = '1' then
+                                       STATES <= S1;
+                               else
+                                       STATES <= S0;
+                               end if;
+
+                       when S1 =>
+                               STATES <= S2;
+
+                       when S2 =>
+                               STATES <= S3;
+
+                       when S3 =>
+                               STATES <= S4;
+
+                       when S4 =>
+                               if SYNC_R_FIFO_FFn = '1' then
+                                       STATES <= S5;
+                               else
+                                       STATES <= S4;
+                               end if;
+
+                       when S5 =>
+                               STATES <= S6;
+
+                       when S6 =>
+                               STATES <= S7;
+
+                       when S7 =>
+                               STATES <= S0;
+
+                       when others =>
+                               STATES <= S0;
+
+                        end case; -- STATES
+                end if; -- RESET
+        end if; -- PCI_CLOCK
+end process; -- PROCESS
+
+ --************************************************************
+ --*** ZUWEISUNG signal/out <= STATES ***
+ --************************************************************
+
+HELP_0 <= STATES(4);
+HELP_1 <= STATES(3);
+SIG_LOAD <= STATES(2);
+R_FIFO_WRITEn <= STATES(1);
+S_FIFO_READn <= STATES(0);
+
+R_FIFO_D_IN <= REG;
+
+end architecture CONNECTING_FSM_DESIGN;