X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/377c02420489dd18db3ce053a075d7eca4ae799b..30273618403fd6512926c89f999f97b4722e1709:/dhwk/source/Verg_4.vhd

diff --git a/dhwk/source/Verg_4.vhd b/dhwk/source/Verg_4.vhd
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--- a/dhwk/source/Verg_4.vhd
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--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: VERG_4.VHD
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity VERG_4 is
-	port
-	(
- 	IN_A		:in		std_logic_vector(3 downto 0);
- 	IN_B		:in		std_logic_vector(3 downto 0);
-	GLEICH	:out	std_logic
-	);
-end entity VERG_4 ;
-
-architecture VERG_4_DESIGN of VERG_4 is
-
-begin
-
-	process (IN_A,IN_B) 
-	begin 
-
-		if			IN_A	=	IN_B	then	GLEICH	<=	'1';
-			else											GLEICH	<=	'0';   
-		end if;
-
-	end process;
-
-end architecture VERG_4_DESIGN;
-