X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/377c02420489dd18db3ce053a075d7eca4ae799b..a76e12bdfc68f955f1cedd0c928fba9372a55d07:/dhwk/source/top.vhd diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd index 2dc252a..e2f307c 100644 --- a/dhwk/source/top.vhd +++ b/dhwk/source/top.vhd @@ -8,7 +8,7 @@ USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; -entity TOP is +entity dhwk is Port ( KONST_1 : In std_logic; PCI_CBEn : In std_logic_vector (3 downto 0); PCI_CLOCK : In std_logic; @@ -16,18 +16,14 @@ entity TOP is PCI_IDSEL : In std_logic; PCI_IRDYn : In std_logic; PCI_RSTn : In std_logic; - R_EFn : In std_logic; - R_FFn : In std_logic; - R_FIFO_Q_OUT : In std_logic_vector (7 downto 0); - R_HFn : In std_logic; - S_EFn : In std_logic; - S_FFn : In std_logic; - S_FIFO_Q_OUT : In std_logic_vector (7 downto 0); - S_HFn : In std_logic; - SERIAL_IN : In std_logic; - SPC_RDY_IN : In std_logic; +-- SERIAL_IN : In std_logic; +-- SPC_RDY_IN : In std_logic; TAST_RESn : In std_logic; TAST_SETn : In std_logic; + LED_2 : out std_logic; + LED_3 : out std_logic; + LED_4 : out std_logic; + LED_5 : out std_logic; PCI_AD : InOut std_logic_vector (31 downto 0); PCI_PAR : InOut std_logic; PCI_DEVSELn : Out std_logic; @@ -36,24 +32,14 @@ entity TOP is PCI_SERRn : Out std_logic; PCI_STOPn : Out std_logic; PCI_TRDYn : Out std_logic; - R_FIFO_D_IN : Out std_logic_vector (7 downto 0); - R_FIFO_READn : Out std_logic; - R_FIFO_RESETn : Out std_logic; - R_FIFO_RTn : Out std_logic; - R_FIFO_WRITEn : Out std_logic; - S_FIFO_D_IN : Out std_logic_vector (7 downto 0); - S_FIFO_READn : Out std_logic; - S_FIFO_RESETn : Out std_logic; - S_FIFO_RTn : Out std_logic; - S_FIFO_WRITEn : Out std_logic; - SERIAL_OUT : Out std_logic; - SPC_RDY_OUT : Out std_logic; +-- SERIAL_OUT : Out std_logic; +-- SPC_RDY_OUT : Out std_logic; TB_IDSEL : Out std_logic; TB_nDEVSEL : Out std_logic; TB_nINTA : Out std_logic ); -end TOP; +end dhwk; -architecture SCHEMATIC of TOP is +architecture SCHEMATIC of dhwk is SIGNAL gnd : std_logic := '0'; SIGNAL vcc : std_logic := '1'; @@ -82,6 +68,32 @@ architecture SCHEMATIC of TOP is signal READ_SEL : std_logic_vector (1 downto 0); signal AD_REG : std_logic_vector (31 downto 0); signal REG_OUT_XX7 : std_logic_vector (7 downto 0); + signal R_EFn : std_logic; + signal R_FFn : std_logic; + signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0); + signal R_HFn : std_logic; + signal S_EFn : std_logic; + signal S_FFn : std_logic; + signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0); + signal S_HFn : std_logic; + signal R_FIFO_D_IN : std_logic_vector (7 downto 0); + signal R_FIFO_READn : std_logic; + signal R_FIFO_RESETn : std_logic; + signal R_FIFO_RTn : std_logic; + signal R_FIFO_WRITEn : std_logic; + signal S_FIFO_D_IN : std_logic_vector (7 downto 0); + signal S_FIFO_READn : std_logic; + signal S_FIFO_RESETn : std_logic; + signal S_FIFO_RTn : std_logic; + signal S_FIFO_WRITEn : std_logic; + signal SERIAL_IN : std_logic; + signal SPC_RDY_IN : std_logic; + signal SERIAL_OUT : std_logic; + signal SPC_RDY_OUT : std_logic; + signal watch : std_logic; + signal control0 : std_logic_vector(35 downto 0); + signal data : std_logic_vector(35 downto 0); + signal trig0 : std_logic_vector(7 downto 0); component MESS_1_TB Port ( DEVSELn : In std_logic; @@ -157,6 +169,7 @@ architecture SCHEMATIC of TOP is SERIAL_OUT : Out std_logic; SPC_RDY_OUT : Out std_logic; SR_ERROR : Out std_logic; + PAR_SER_IN : Out std_logic_vector (7 downto 0); SYNC_FLAG : Out std_logic_vector (7 downto 0) ); end component; @@ -197,7 +210,68 @@ architecture SCHEMATIC of TOP is WRITE_XX7_6 : Out std_logic ); end component; +component fifo_generator_v3_2 + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(7 downto 0); + rd_en: IN std_logic; + rst: IN std_logic; + wr_en: IN std_logic; + almost_empty: OUT std_logic; + almost_full: OUT std_logic; + dout: OUT std_logic_VECTOR(7 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + prog_full: OUT std_logic); +end component; + +component icon +port + ( + control0 : out std_logic_vector(35 downto 0) + ); +end component; + + component ila + port + ( + control : in std_logic_vector(35 downto 0); + clk : in std_logic; + data : in std_logic_vector(35 downto 0); + trig0 : in std_logic_vector(7 downto 0) + ); + end component; + + begin + SERIAL_IN <= SERIAL_OUT; + SPC_RDY_IN <= SPC_RDY_OUT; + LED_2 <= TAST_RESn; + LED_3 <= TAST_SETn; + LED_4 <= '0'; + LED_5 <= not watch; + PCI_INTAn <= watch; + trig0(7 downto 0) <= (0 => watch, others => '0'); + data(0) <= watch; + + data(1) <= R_EFn; + data(2) <= R_HFn; + data(3) <= R_FFn; + data(4) <= R_FIFO_READn; + data(5) <= R_FIFO_RESETn; + data(6) <= R_FIFO_RTn; + data(7) <= R_FIFO_WRITEn; + data(8) <= S_EFn; + data(9) <= S_HFn; + data(10) <= S_FFn; + data(11) <= S_FIFO_READn; + data(12) <= S_FIFO_RESETn; + data(13) <= S_FIFO_RTn; + data(14) <= S_FIFO_WRITEn; + data(15) <= SERIAL_IN; + data(16) <= SPC_RDY_IN; + data(17) <= SERIAL_OUT; + data(18) <= SPC_RDY_OUT; I19 : MESS_1_TB Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1, @@ -218,7 +292,7 @@ begin READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0), TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn, TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0), - INTAn=>INTAn, PCI_INTAn=>PCI_INTAn ); + INTAn=>INTAn, PCI_INTAn=>watch); I14 : FIFO_CONTROL Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR, FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1, @@ -239,6 +313,7 @@ begin S_FIFO_RETRANSMITn=>S_FIFO_RTn, S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT, SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR, + PAR_SER_IN(7 downto 0)=>data(26 downto 19), SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) ); I1 : PCI_TOP Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0), @@ -267,4 +342,42 @@ begin WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4, WRITE_XX7_6=>WRITE_XX7_6 ); +receive_fifo : fifo_generator_v3_2 + port map ( + clk => PCI_CLOCK, + din => R_FIFO_D_IN, + rd_en => not R_FIFO_READn, + rst => not R_FIFO_RESETn, + wr_en => not R_FIFO_WRITEn, + dout => R_FIFO_Q_OUT, + empty => R_EFn, + full => R_FFn, + prog_full => R_HFn); + +send_fifo : fifo_generator_v3_2 + port map ( + clk => PCI_CLOCK, + din => S_FIFO_D_IN, + rd_en => not S_FIFO_READn, + rst => not S_FIFO_RESETn, + wr_en => not S_FIFO_WRITEn, + dout => S_FIFO_Q_OUT, + empty => S_EFn, + full => S_FFn, + prog_full => S_HFn); + + i_icon : icon + port map + ( + control0 => control0 + ); + + i_ila : ila + port map + ( + control => control0, + clk => PCI_CLOCK, + data => data, + trig0 => trig0 + ); end SCHEMATIC;