X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/3ddb8de34b131fc13c45bd5c5c33264fb127a141..d452afd57d3469271a8532a9271ed7c14a53a427:/dhwk/source/Addr_regi.vhd

diff --git a/dhwk/source/Addr_regi.vhd b/dhwk/source/Addr_regi.vhd
deleted file mode 100644
index 143c7b5..0000000
--- a/dhwk/source/Addr_regi.vhd
+++ /dev/null
@@ -1,43 +0,0 @@
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: ADDR_REG.VHD
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity ADDR_REGI is
-	port
-	(
-	PCI_CLOCK			:in		std_logic;
-	PCI_RSTn			:in		std_logic;
-	LOAD_ADDR_REG	:in		std_logic;
-	AD_REG				:in		std_logic_vector (31 downto 0);
-	ADDR_REG			:out	std_logic_vector (31 downto 0)
-  );
-end entity ADDR_REGI;
-
-architecture ADDR_REGI_DESIGN of ADDR_REGI is
-
-	signal	REG_ADDR	:std_logic_vector (31 downto 0); 
-
-begin 
-
-	process (PCI_CLOCK, PCI_RSTn) 
-	begin
-		if	PCI_RSTn = '0'	then	REG_ADDR	<= X"00000000";
-
-		elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
-
-			if LOAD_ADDR_REG = '1' then
-						REG_ADDR	<=	AD_REG;
-
-			else	REG_ADDR	<=	REG_ADDR;
-			end if;
-
-		end if;
-	end process;
-
-	ADDR_REG	<=	REG_ADDR;
-
-end architecture ADDR_REGI_DESIGN;