X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/3ddb8de34b131fc13c45bd5c5c33264fb127a141..d452afd57d3469271a8532a9271ed7c14a53a427:/dhwk/source/io_mux_reg.vhd?ds=sidebyside

diff --git a/dhwk/source/io_mux_reg.vhd b/dhwk/source/io_mux_reg.vhd
index 38f2356..564d8bb 100644
--- a/dhwk/source/io_mux_reg.vhd
+++ b/dhwk/source/io_mux_reg.vhd
@@ -38,7 +38,7 @@ architecture SCHEMATIC of IO_MUX_REG is
    signal  IO_DATA : std_logic_vector (31 downto 0);
    signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
 
-   component ADDR_REGI
+   component ADDRESS_REGISTER
       Port (  AD_REG : In    std_logic_vector (31 downto 0);
              LOAD_ADDR_REG : In    std_logic;
              PCI_CLOCK : In    std_logic;
@@ -77,7 +77,7 @@ begin
 
    AD_REG <= AD_REG_DUMMY;
 
-   I5 : ADDR_REGI
+   I5 : ADDRESS_REGISTER
       Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
                  LOAD_ADDR_REG=>LOAD_ADDR_REG, PCI_CLOCK=>PCI_CLOCK,
                  PCI_RSTn=>PCI_RSTn,