X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/40a1f26c3a09dbd1f71f4fd7f3aca74f387a09db..361ec26f7bd0c6ecd99a7eac5112d4c61205b82f:/ethernet/source/ethernet/eth_defines.v

diff --git a/ethernet/source/ethernet/eth_defines.v b/ethernet/source/ethernet/eth_defines.v
index 26001f5..685b5f5 100644
--- a/ethernet/source/ethernet/eth_defines.v
+++ b/ethernet/source/ethernet/eth_defines.v
@@ -41,8 +41,14 @@
 // CVS Revision History
 //
 // $Log: eth_defines.v,v $
-// Revision 1.1  2007-03-20 17:50:56  sithglan
-// add shit
+// Revision 1.3  2007-03-20 22:39:24  sithglan
+// WISHBONE B3
+//
+// Revision 1.2  2007/03/20 22:17:38  sithglan
+// += use xilinx block ram for ethernet
+//
+// Revision 1.1  2007/03/19 16:44:04  sithglan
+// lot of new files
 //
 // Revision 1.34  2005/02/21 12:48:06  igorm
 // Warning fixes.
@@ -186,7 +192,7 @@
 `define ETH_MBIST_CTRL_WIDTH 3        // width of MBIST control bus
 
 // Ethernet implemented in Xilinx Chips (uncomment following lines)
-// `define ETH_FIFO_XILINX             // Use Xilinx distributed ram for tx and rx fifo
+`define ETH_FIFO_XILINX             // Use Xilinx distributed ram for tx and rx fifo
 // `define ETH_XILINX_RAMB4            // Selection of the used memory for Buffer descriptors
                                       // Core is going to be implemented in Virtex FPGA and contains Virtex 
                                       // specific elements. 
@@ -334,8 +340,7 @@
 `define ETH_BURST_CNT_WIDTH    3    // The counter must be width enough to count to ETH_BURST_LENGTH
 
 // WISHBONE interface is Revision B3 compliant (uncomment when needed)
-//`define ETH_WISHBONE_B3
-
+`define ETH_WISHBONE_B3
 
 // Following defines are needed when eth_cop.v is used. Otherwise they may be deleted.
 `define ETH_BASE              32'hd0000000