X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/40a1f26c3a09dbd1f71f4fd7f3aca74f387a09db..e1742f3e6ca6886a17fa8db44e2b4d11a8013a4e:/ethernet/source/pci/pci_user_constants.v

diff --git a/ethernet/source/pci/pci_user_constants.v b/ethernet/source/pci/pci_user_constants.v
index 22ef572..f17bcd0 100644
--- a/ethernet/source/pci/pci_user_constants.v
+++ b/ethernet/source/pci/pci_user_constants.v
@@ -39,7 +39,13 @@
 // CVS Revision History
 //
 // $Log: pci_user_constants.v,v $
-// Revision 1.1  2007-03-20 17:50:56  sithglan
+// Revision 1.3  2007-03-21 11:53:06  sithglan
+// enable address translation
+//
+// Revision 1.2  2007/03/20 20:56:19  sithglan
+// changes
+//
+// Revision 1.1  2007/03/20 17:50:56  sithglan
 // add shit
 //
 // Revision 1.15  2004/08/19 15:27:34  mihad
@@ -108,14 +114,14 @@
 
 `define WBW_ADDR_LENGTH 4
 `define WBR_ADDR_LENGTH 4
-`define PCIW_ADDR_LENGTH 3
-`define PCIR_ADDR_LENGTH 3
+`define PCIW_ADDR_LENGTH 4
+`define PCIR_ADDR_LENGTH 4
 
-//`define FPGA
-//`define XILINX
+`define FPGA
+`define XILINX
 
-`define WB_RAM_DONT_SHARE
-`define PCI_RAM_DONT_SHARE
+//`define WB_RAM_DONT_SHARE
+//`define PCI_RAM_DONT_SHARE
 
 `ifdef FPGA
     `ifdef XILINX
@@ -156,7 +162,7 @@
 // allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
 // you have to define a number of minimum sized image and enlarge others by specifying different address mask.
 // smaller the number here, faster the decoder operation
-`define PCI_NUM_OF_DEC_ADDR_LINES 24
+`define PCI_NUM_OF_DEC_ADDR_LINES 19
 
 // no. of PCI Target IMAGES
 // - PCI provides 6 base address registers for image implementation.
@@ -231,7 +237,7 @@
 // ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
 // WB Image 1 is always implemented and user doesnt need to specify its definition
 // WB images' 2 through 5 implementation by defining each one.
-`define WB_IMAGE2
+//`define WB_IMAGE2
 //`define WB_IMAGE3
 //`define WB_IMAGE4
 //`define WB_IMAGE5
@@ -278,7 +284,7 @@
 // addresses will pass through bridge unchanged, regardles of address translation enable bits.
 // Address translation also slows down the decoding
 //When  ADDR_TRAN_IMPL this define is present then adress translation is enabled after reset.
-//`define ADDR_TRAN_IMPL
+`define ADDR_TRAN_IMPL
 
 // decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
 // slower decode speed can be used, to provide enough time for address to be decoded.
@@ -307,11 +313,11 @@ capable device
 	Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
 	together by application.
 -----------------------------------------------------------------------------------------------------------*/
-`define HEADER_VENDOR_ID        16'h1895
-`define HEADER_DEVICE_ID        16'h0001
+`define HEADER_VENDOR_ID        16'h4242
+`define HEADER_DEVICE_ID        16'h2323
 `define HEADER_REVISION_ID      8'h01
-`define HEADER_SUBSYS_VENDOR_ID 16'h1895
-`define HEADER_SUBSYS_ID        16'h0001
+`define HEADER_SUBSYS_VENDOR_ID 16'h4242
+`define HEADER_SUBSYS_ID        16'h2323
 `define HEADER_MAX_LAT          8'h1a
 `define HEADER_MIN_GNT          8'h08