X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/40a64bf197a313eb87943d84a985e0d90086729e..f5e6af20ca64efec2eea066b18d466f73d20bcab:/dhwk/vio.xco

diff --git a/dhwk/vio.xco b/dhwk/vio.xco
deleted file mode 100644
index 7575b90..0000000
--- a/dhwk/vio.xco
+++ /dev/null
@@ -1,35 +0,0 @@
-# BEGIN Project Options
-SET addpads = False
-SET asysymbol = False
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
-SET designentry = VHDL
-SET device = xc3s1500
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = False
-SET foundationsym = False
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = False
-SET simulationfiles = Structural
-SET speedgrade = -4
-SET verilogsim = False
-SET vhdlsim = True
-# END Project Options
-# BEGIN Select
-SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.02.a
-# END Select
-# BEGIN Parameters
-CSET asynchronous_input_port_width=4
-CSET asynchronous_output_port_width=8
-CSET component_name=vio
-CSET enable_asynchronous_input_port=true
-CSET enable_asynchronous_output_port=false
-CSET enable_synchronous_input_port=false
-CSET enable_synchronous_output_port=true
-CSET invert_clock_input=false
-CSET synchronous_input_port_width=8
-CSET synchronous_output_port_width=1
-# END Parameters
-GENERATE