X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/4d7b5fdda466a23785cf991038933df79abf4604..c8b3e197e6ec554806e722b220010e7c03830dea:/ethernet/source/top.vhd

diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd
index 8c90690..6530c18 100644
--- a/ethernet/source/top.vhd
+++ b/ethernet/source/top.vhd
@@ -154,6 +154,21 @@ PORT(
         );
 END COMPONENT;
 
+component icon
+port (
+	control0 : out std_logic_vector(35 downto 0)
+	);
+end component;
+
+component ila
+port (
+	control : in std_logic_vector(35 downto 0);
+	clk : in std_logic;
+	data : in std_logic_vector(63 downto 0);
+	trig0 : in std_logic_vector(31 downto 0)
+	);
+end component;
+
 signal pci_rst_o : std_logic;
 signal pci_rst_oe_o : std_logic;
 signal pci_inta_o : std_logic;
@@ -209,6 +224,11 @@ signal wbm_adr_o : std_logic_vector(31 downto 0);
 signal m_wb_cti_o : std_logic_vector(2 downto 0);
 signal m_wb_bte_o : std_logic_vector(1 downto 0);
 
+signal control0 : std_logic_vector(35 downto 0);
+signal data : std_logic_vector(63 downto 0);
+signal trig0 : std_logic_vector(31 downto 0);
+
+
 BEGIN
 
 PCI_RSTn    <= pci_rst_o    when (pci_rst_oe_o = '1')     else 'Z';
@@ -234,6 +254,16 @@ end generate;
 
 wb_adr_i <= wbm_adr_o (11 downto 2);
 
+wb_clk_i <= PCI_CLOCK;
+
+data(31 downto 0) <= wbm_adr_o;
+data(63 downto 32) <= (others => '0');
+
+trig(31 downto 0) <= (
+	0 => wb_stb_i,
+	others => '0'
+);
+
 Inst_pci_bridge32: pci_bridge32 PORT MAP(
         wb_clk_i => wb_clk_i ,
         wb_rst_i => '0',
@@ -346,4 +376,17 @@ Inst_eth_top: eth_top PORT MAP(
         int_o => int_o
 );
 
+i_icon : icon
+port map (
+	control0 => control0
+	);
+
+i_ila : ila
+port map (
+	control => control0,
+	clk => PCI_CLOCK,
+	data => data,
+	trig0 => trig0
+	);
+
 end architecture ethernet_arch;