X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/522948a68a77f80b071425e23c7c7ae6a610911e..30273618403fd6512926c89f999f97b4722e1709:/dhwk_old/source/top_dhwk.vhd?ds=sidebyside

diff --git a/dhwk_old/source/top_dhwk.vhd b/dhwk_old/source/top_dhwk.vhd
index 98add0f..13de352 100644
--- a/dhwk_old/source/top_dhwk.vhd
+++ b/dhwk_old/source/top_dhwk.vhd
@@ -1,43 +1,8 @@
---+-------------------------------------------------------------------------------------------------+
---|																									|
---|  File:			top.vhd                       		                                   	|
---|																									|
---|  Components:	pci32lite.vhd                                                                   |
---|		            pciwbsequ.vhd           														|
---|		            pcidmux.vhd           															|
---|		            pciregs.vhd           															|
---|		            pcipargen.vhd          															|
---|		            -- Libs --             															|
---|		            ona.vhd		          															|
---|																									|
---|	 Description:	RS1 PCI Demo : (TOP) Main file.						 				        |
---| 				 																				|
---|					                														        |
---|																									|
---+-------------------------------------------------------------------------------------------------+
---|																									|
---|  Revision history :																				|
---|  Date 		  Version	Author	Description														|
---|																									|
---|																									|
---|  To do:																 							|
---|																									|
---+-------------------------------------------------------------------------------------------------+
-
-
---+-----------------------------------------------------------------------------+
---|									LIBRARIES									|
---+-----------------------------------------------------------------------------+
-
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
---+-----------------------------------------------------------------------------+
---|									ENTITY   									|
---+-----------------------------------------------------------------------------+
-
 entity dhwk is
 port (
 
@@ -69,17 +34,9 @@ port (
 end dhwk;
 
 
---+-----------------------------------------------------------------------------+
---|									ARCHITECTURE								|
---+-----------------------------------------------------------------------------+
-
 architecture dhwk_arch of dhwk is
 
 
---+-----------------------------------------------------------------------------+
---|									COMPONENTS									|
---+-----------------------------------------------------------------------------+
-
 component pci32tlite
 port (
 
@@ -152,49 +109,50 @@ port (
 );
 end component;
 
-component generic_dpram
+component wb_fifo
 port (
-	rclk		: in std_logic;
-	rrst		: in std_logic;
-	rce		: in std_logic;
-	oe		: in std_logic;
-	raddr		: in std_logic_vector(11 downto 0);
-	do		: out std_logic_vector(7 downto 0);
-	wclk		: in std_logic;
-	wrst		: in std_logic;
-	wce		: in std_logic;
-	we		: in std_logic;
-	waddr		: in std_logic_vector(11 downto 0);
-	di		: in std_logic_vector(7 downto 0)
+	clk_i		: in std_logic;
+	nrst_i		: in std_logic;
+	
+	wb_adr_i	: in std_logic_vector(24 downto 1);
+	wb_dat_o	: out std_logic_vector(15 downto 0);
+	wb_dat_i	: in std_logic_vector(15 downto 0);
+	wb_sel_i	: in std_logic_vector(1 downto 0);
+	wb_we_i		: in std_logic;
+	wb_stb_i	: in std_logic;
+	wb_cyc_i	: in std_logic;
+	wb_ack_o	: out std_logic;
+	wb_err_o	: out std_logic;
+	wb_int_o	: out std_logic;
+	
+	fifo_data_i	: in std_logic_vector(7 downto 0);
+	fifo_data_o     : out std_logic_vector(7 downto 0);
+
+	fifo_we_o	: out std_logic;
+	fifo_re_o	: out std_logic
 );
 end component;
 
+signal 	wb_adr :		std_logic_vector(24 downto 1);   
+signal	wb_dat_out :	std_logic_vector(15 downto 0);
+signal 	wb_dat_in :		std_logic_vector(15 downto 0);
+signal	wb_sel :		std_logic_vector(1 downto 0);
+signal  wb_we :			std_logic;
+signal	wb_stb :		std_logic;
+signal	wb_cyc :		std_logic;
+signal	wb_ack :		std_logic;
+signal	wb_err :		std_logic;
+signal	wb_int :		std_logic;
 
---+-----------------------------------------------------------------------------+
---|									CONSTANTS  									|
---+-----------------------------------------------------------------------------+
---+-----------------------------------------------------------------------------+
---|									SIGNALS   									|
---+-----------------------------------------------------------------------------+
+signal fifo_din		: std_logic_vector(7 downto 0);
+signal fifo_dout	: std_logic_vector(7 downto 0);
+signal fifo_we		: std_logic;
+signal fifo_re		: std_logic;
 
-	signal 	wb_adr :		std_logic_vector(24 downto 1);   
-	signal	wb_dat_out :	std_logic_vector(15 downto 0);
- 	signal 	wb_dat_in :		std_logic_vector(15 downto 0);
-	signal	wb_sel :		std_logic_vector(1 downto 0);
- 	signal  wb_we :			std_logic;
-	signal	wb_stb :		std_logic;
-	signal	wb_cyc :		std_logic;
-	signal	wb_ack :		std_logic;
-	signal	wb_err :		std_logic;
-	signal	wb_int :		std_logic;
 
 
 begin
 
---+-----------------------------------------+
---|  PCI Target 							|
---+-----------------------------------------+
-
 u_pci: component pci32tlite
 port map(
     	clk33 =>		PCI_CLK,
@@ -223,11 +181,50 @@ port map(
 		wb_int_i =>		wb_int
 --		debug_init =>	LED3,
 --		debug_access =>	LED2
-		);
+);
+
+my_generic_fifo: component generic_fifo_sc_a
+port map(
+	clk		=> PCI_CLK,
+	rst		=> PCI_nRES,
+	clr		=> '0',
+	din		=> fifo_din,
+	we		=> fifo_we,
+	dout		=> fifo_dout,
+	re		=> fifo_re
+--	full		=> ,
+--	full_r		=> ,
+--	empty		=> ,
+--	empty_r		=> ,
+--	full_n		=> ,
+--	full_n_r	=> ,
+--	empty_n		=> ,
+--	empty_n_r	=> ,
+--	level		=> ,
+);
 
---+-----------------------------------------+
---|  WB-7seg             					|
---+-----------------------------------------+
+my_fifo: component wb_fifo
+port map(
+	clk_i		 => PCI_CLK,
+	nrst_i		 => PCI_nRES,
+
+	wb_adr_i	 => wb_adr,
+	wb_dat_o	 => wb_dat_out,
+	wb_dat_i	 => wb_dat_in,
+	wb_sel_i	 => wb_sel,
+	wb_we_i		 => wb_we,
+	wb_stb_i	 => wb_stb,
+	wb_cyc_i	 => wb_cyc,
+	wb_ack_o	 => wb_ack,
+	wb_err_o	 => wb_err,
+	wb_int_o	 => wb_int,
+
+	fifo_data_i	 => fifo_dout,
+	fifo_data_o      => fifo_din,
+
+	fifo_we_o	 => fifo_we,
+	fifo_re_o	 => fifo_re
+);
 
 my_heartbeat: component heartbeat
 port map(