X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/528d015aa19100f9f97b3469ab7d2aafa43b425e..40a1f26c3a09dbd1f71f4fd7f3aca74f387a09db:/ethernet/source/pci/pci_pci_tpram.v diff --git a/ethernet/source/pci/pci_pci_tpram.v b/ethernet/source/pci/pci_pci_tpram.v new file mode 100644 index 0000000..9db2a75 --- /dev/null +++ b/ethernet/source/pci/pci_pci_tpram.v @@ -0,0 +1,467 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Two-Port Synchronous RAM //// +//// //// +//// This file is part of pci bridge project //// +//// http://www.opencores.org/cvsweb.shtml/pci/ //// +//// //// +//// Description //// +//// This block is a wrapper with common two-port //// +//// synchronous memory interface for different //// +//// types of ASIC and FPGA RAMs. Beside universal memory //// +//// interface it also provides behavioral model of generic //// +//// two-port synchronous RAM. //// +//// It should be used in all OPENCORES designs that want to be //// +//// portable accross different target technologies and //// +//// independent of target memory. //// +//// //// +//// Supported ASIC RAMs are: //// +//// - Artisan Double-Port Sync RAM //// +//// - Avant! Two-Port Sync RAM (*) //// +//// - Virage 2-port Sync RAM //// +//// //// +//// Supported FPGA RAMs are: //// +//// - Xilinx Virtex RAMB4_S16_S16 //// +//// //// +//// To Do: //// +//// - fix Avant! //// +//// - xilinx rams need external tri-state logic //// +//// - add additional RAMs (Altera, VS etc) //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// - Miha Dolenc, mihad@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_pci_tpram.v,v $ +// Revision 1.1 2007-03-20 17:50:56 sithglan +// add shit +// +// Revision 1.4 2004/08/19 15:27:34 mihad +// Changed minimum pci image size to 256 bytes because +// of some PC system problems with size of IO images. +// +// Revision 1.3 2003/10/17 09:11:52 markom +// mbist signals updated according to newest convention +// +// Revision 1.2 2003/08/14 13:06:03 simons +// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. +// +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.7 2002/10/18 03:36:37 tadejm +// Changed wrong signal name mbist_sen into mbist_ctrl_i. +// +// Revision 1.6 2002/10/17 22:51:08 tadejm +// Changed BIST signals for RAMs. +// +// Revision 1.5 2002/10/11 10:09:01 mihad +// Added additional testcase and changed rst name in BIST to trst +// +// Revision 1.4 2002/10/08 17:17:06 mihad +// Added BIST signals for RAMs. +// +// Revision 1.3 2002/09/30 17:22:27 mihad +// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! +// +// Revision 1.2 2002/08/19 16:51:36 mihad +// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives +// +// Revision 1.1 2002/02/01 14:43:31 mihad +// *** empty log message *** +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "pci_constants.v" + +module pci_pci_tpram +( + // Generic synchronous two-port RAM interface + clk_a, + rst_a, + ce_a, + we_a, + oe_a, + addr_a, + di_a, + do_a, + clk_b, + rst_b, + ce_b, + we_b, + oe_b, + addr_b, + di_b, + do_b +`ifdef PCI_BIST + , + // debug chain signals + mbist_si_i, // bist scan serial in + mbist_so_o, // bist scan serial out + mbist_ctrl_i // bist chain shift control +`endif +); + +// +// Default address and data buses width +// +parameter aw = 8; +parameter dw = 40; + +// +// Generic synchronous two-port RAM interface +// +input clk_a; // Clock +input rst_a; // Reset +input ce_a; // Chip enable input +input we_a; // Write enable input +input oe_a; // Output enable input +input [aw-1:0] addr_a; // address bus inputs +input [dw-1:0] di_a; // input data bus +output [dw-1:0] do_a; // output data bus +input clk_b; // Clock +input rst_b; // Reset +input ce_b; // Chip enable input +input we_b; // Write enable input +input oe_b; // Output enable input +input [aw-1:0] addr_b; // address bus inputs +input [dw-1:0] di_b; // input data bus +output [dw-1:0] do_b; // output data bus + +`ifdef PCI_BIST +// debug chain signals +input mbist_si_i; // bist scan serial in +output mbist_so_o; // bist scan serial out +input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control +`endif + +// +// Internal wires and registers +// + +`ifdef PCI_VS_STP + `define PCI_PCI_RAM_SELECTED + `ifdef PCI_BIST + vs_hdtp_64x40_bist i_vs_hdtp_64x40_bist + `else + vs_hdtp_64x40 i_vs_hdtp_64x40 + `endif + ( + .RCK (clk_b), + .WCK (clk_a), + .RADR (addr_b), + .WADR (addr_a), + .DI (di_a), + .DOUT (do_b), + .REN (1'b0), + .WEN (!we_a) + `ifdef PCI_BIST + , + // debug chain signals + .mbist_si_i (mbist_si_i), + .mbist_so_o (mbist_so_o), + .mbist_ctrl_i (mbist_ctrl_i) + `endif + ); + + assign do_a = 0 ; +`endif + +`ifdef PCI_ARTISAN_SDP + `define PCI_PCI_RAM_SELECTED + // + // Instantiation of ASIC memory: + // + // Artisan Synchronous Double-Port RAM (ra2sh) + // + `ifdef PCI_BIST + art_hsdp_64x40_bist /*#(dw, 1<