X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/528d015aa19100f9f97b3469ab7d2aafa43b425e..40a1f26c3a09dbd1f71f4fd7f3aca74f387a09db:/ethernet/source/top.vhd diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd new file mode 100644 index 0000000..af81bdd --- /dev/null +++ b/ethernet/source/top.vhd @@ -0,0 +1,303 @@ +entity top is +PORT( + PCI_AD : INOUT std_logic_vector(31 downto 0); + PCI_CLOCK : IN std_logic; + PCI_IDSEL : IN std_logic; + PCI_CBEn : INOUT std_logic_vector (3 downto 0); + PCI_FRAMEn : INOUT std_logic; + PCI_IRDYn : INOUT std_logic; + PCI_RSTn : INOUT std_logic; + PCI_DEVSELn : INOUT std_logic; + PCI_INTAn : INOUT std_logic; + PCI_PERRn : INOUT std_logic; + PCI_SERRn : INOUT std_logic; + PCI_STOPn : INOUT std_logic; + PCI_TRDYn : INOUT std_logic; + PCI_PAR : INOUT std_logic; + PCI_REQn : OUT std_logic; + PCI_GNTn : IN std_logic; + + MTX_CLK_PAD_I : IN std_logic; + MTXD_PAD_O : OUT std_logic_vector (3 downto 0); + MTXEN_PAD_O : OUT std_logic; + MRX_CLK_PAD_I : IN std_logic; + MRXD_PAD_I : IN std_logic_vector (3 downto 0); + MRXDV_PAD_I : IN std_logic; + MRXERR_PAD_I : IN std_logic; + MCOLL_PAD_I : IN std_logic; + MCRS_PAD_I : IN std_logic; + MD_PAD_IO : INOUT std_logic; + MDC_PAD_O : OUT std_logic; +); +end top; + +architecture bla of top is + +COMPONENT eth_top +PORT( + wb_clk_i : IN std_logic; + wb_rst_i : IN std_logic; + wb_dat_i : IN std_logic_vector(31 downto 0); + wb_adr_i : IN std_logic_vector(11 downto 2); + wb_sel_i : IN std_logic_vector(3 downto 0); + wb_we_i : IN std_logic; + wb_cyc_i : IN std_logic; + wb_stb_i : IN std_logic; + m_wb_dat_i : IN std_logic_vector(31 downto 0); + m_wb_ack_i : IN std_logic; + m_wb_err_i : IN std_logic; + mtx_clk_pad_i : IN std_logic; + mrx_clk_pad_i : IN std_logic; + mrxd_pad_i : IN std_logic_vector(3 downto 0); + mrxdv_pad_i : IN std_logic; + mrxerr_pad_i : IN std_logic; + mcoll_pad_i : IN std_logic; + mcrs_pad_i : IN std_logic; + md_pad_i : IN std_logic; + wb_dat_o : OUT std_logic_vector(31 downto 0); + wb_ack_o : OUT std_logic; + wb_err_o : OUT std_logic; + m_wb_adr_o : OUT std_logic_vector(31 downto 0); + m_wb_sel_o : OUT std_logic_vector(3 downto 0); + m_wb_we_o : OUT std_logic; + m_wb_dat_o : OUT std_logic_vector(31 downto 0); + m_wb_cyc_o : OUT std_logic; + m_wb_stb_o : OUT std_logic; + mtxd_pad_o : OUT std_logic_vector(3 downto 0); + mtxen_pad_o : OUT std_logic; + mtxerr_pad_o : OUT std_logic; + mdc_pad_o : OUT std_logic; + md_pad_o : OUT std_logic; + md_padoe_o : OUT std_logic; + int_o : OUT std_logic + ); +END COMPONENT; + +COMPONENT pci_bridge32 +PORT( + wb_clk_i : IN std_logic; + wb_rst_i : IN std_logic; + wb_int_i : IN std_logic; + wbs_adr_i : IN std_logic_vector(31 downto 0); + wbs_dat_i : IN std_logic_vector(31 downto 0); + wbs_sel_i : IN std_logic_vector(3 downto 0); + wbs_cyc_i : IN std_logic; + wbs_stb_i : IN std_logic; + wbs_we_i : IN std_logic; + wbs_cti_i : IN std_logic_vector(2 downto 0); + wbs_bte_i : IN std_logic_vector(1 downto 0); + wbm_dat_i : IN std_logic_vector(31 downto 0); + wbm_ack_i : IN std_logic; + wbm_rty_i : IN std_logic; + wbm_err_i : IN std_logic; + pci_clk_i : IN std_logic; + pci_rst_i : IN std_logic; + pci_inta_i : IN std_logic; + pci_gnt_i : IN std_logic; + pci_frame_i : IN std_logic; + pci_irdy_i : IN std_logic; + pci_idsel_i : IN std_logic; + pci_devsel_i : IN std_logic; + pci_trdy_i : IN std_logic; + pci_stop_i : IN std_logic; + pci_ad_i : IN std_logic_vector(31 downto 0); + pci_cbe_i : IN std_logic_vector(3 downto 0); + pci_par_i : IN std_logic; + pci_perr_i : IN std_logic; + wb_rst_o : OUT std_logic; + wb_int_o : OUT std_logic; + wbs_dat_o : OUT std_logic_vector(31 downto 0); + wbs_ack_o : OUT std_logic; + wbs_rty_o : OUT std_logic; + wbs_err_o : OUT std_logic; + wbm_adr_o : OUT std_logic_vector(31 downto 0); + wbm_dat_o : OUT std_logic_vector(31 downto 0); + wbm_sel_o : OUT std_logic_vector(3 downto 0); + wbm_cyc_o : OUT std_logic; + wbm_stb_o : OUT std_logic; + wbm_we_o : OUT std_logic; + wbm_cti_o : OUT std_logic_vector(2 downto 0); + wbm_bte_o : OUT std_logic_vector(1 downto 0); + pci_rst_o : OUT std_logic; + pci_inta_o : OUT std_logic; + pci_rst_oe_o : OUT std_logic; + pci_inta_oe_o : OUT std_logic; + pci_req_o : OUT std_logic; + pci_req_oe_o : OUT std_logic; + pci_frame_o : OUT std_logic; + pci_frame_oe_o : OUT std_logic; + pci_irdy_oe_o : OUT std_logic; + pci_devsel_oe_o : OUT std_logic; + pci_trdy_oe_o : OUT std_logic; + pci_stop_oe_o : OUT std_logic; + pci_ad_oe_o : OUT std_logic_vector(31 downto 0); + pci_cbe_oe_o : OUT std_logic_vector(3 downto 0); + pci_irdy_o : OUT std_logic; + pci_devsel_o : OUT std_logic; + pci_trdy_o : OUT std_logic; + pci_stop_o : OUT std_logic; + pci_ad_o : OUT std_logic_vector(31 downto 0); + pci_cbe_o : OUT std_logic_vector(3 downto 0); + pci_par_o : OUT std_logic; + pci_par_oe_o : OUT std_logic; + pci_perr_o : OUT std_logic; + pci_perr_oe_o : OUT std_logic; + pci_serr_o : OUT std_logic; + pci_serr_oe_o : OUT std_logic + ); +END COMPONENT; + +signal pci_rst_o : std_logic; +signal pci_rst_oe_o : std_logic; +signal pci_inta_o : std_logic; +signal pci_inta_oe_o : std_logic; +signal pci_req_o : std_logic; +signal pci_req_oe_o : std_logic; +signal pci_frame_o : std_logic; +signal pci_frame_oe_o : std_logic; +signal pci_irdy_o : std_logic; +signal pci_irdy_oe_o : std_logic; +signal pci_devsel_o : std_logic; +signal pci_devsel_oe_o : std_logic; +signal pci_trdy_o : std_logic; +signal pci_trdy_oe_o : std_logic; +signal pci_stop_o : std_logic; +signal pci_stop_oe_o : std_logic; +signal pci_par_o : std_logic; +signal pci_par_oe_o : std_logic; +signal pci_perr_o : std_logic; +signal pci_perr_oe_o : std_logic; +signal pci_serr_o : std_logic; +signal pci_serr_oe_o : std_logic; +signal pci_ad_oe_o : std_logic; +signal pci_cbe_oe_o : std_logic; +signal pci_ad_o : std_logic_vector (31 downto 0); +signal pci_cbe_o : std_logic_vector (3 downto 0); + +BEGIN + +PCI_RSTn <= if (pci_rst_oe_o = '1') then pci_rst_o else 'Z'; +PCI_INTAn <= if (pci_inta_oe_o = '1') then pci_inta_o else 'Z'; +PCI_REQn <= if (pci_req_oe_o = '1') then pci_req_o else 'Z'; +PCI_FRAMEn <= if (pci_frame_oe_o '1') then pci_frame_o else 'Z'; +PCI_IRDYn <= if (pci_irdy_oe_o = '1') then pci_irdy_o else 'Z'; +PCI_DEVSELn <= if (pci_devsel_oe_o = '1') then pci_devsel_o else 'Z'; +PCI_TRDYn <= if (pci_trdy_oe_o = '1') then pci_trdy_o else 'Z'; +PCI_STOPn <= if (pci_stop_oe_o = '1') then pci_stop_o else 'Z'; +PCI_AD <= if (pci_ad_oe_o = '1') then pci_ad_o else (others => 'Z'); +PCI_CBEn <= if (pci_cbe_oe_o = '1') then pci_cbe_o else (others => 'Z'); +PCI_PAR <= if (pci_par_oe_o = '1') then pci_par_o else 'Z'; +PCI_PERRn <= if (pci_perr_oe_o = '1') then pci_perr_o else 'Z'; +PCI_SERRn <= if (pci_serr_oe_o = '1') then pci_serr_o else 'Z'; + +Inst_pci_bridge32: pci_bridge32 PORT MAP( + wb_clk_i => , + wb_rst_i => , + wb_rst_o => , + wb_int_i => , + wb_int_o => , + wbs_adr_i => , + wbs_dat_i => , + wbs_dat_o => , + wbs_sel_i => , + wbs_cyc_i => , + wbs_stb_i => , + wbs_we_i => , + wbs_cti_i => , + wbs_bte_i => , + wbs_ack_o => , + wbs_rty_o => , + wbs_err_o => , + wbm_adr_o => , + wbm_dat_i => , + wbm_dat_o => , + wbm_sel_o => , + wbm_cyc_o => , + wbm_stb_o => , + wbm_we_o => , + wbm_cti_o => , + wbm_bte_o => , + wbm_ack_i => , + wbm_rty_i => , + wbm_err_i => , + pci_clk_i => PCI_CLOCK, + pci_rst_i => PCI_RSTn, + pci_rst_o => pci_rst_o , + pci_rst_oe_o => pci_rst_oe_o, + pci_inta_i => PCI_INTAn, + pci_inta_o => pci_inta_o, + pci_inta_oe_o => pci_inta_oe_o, + pci_req_o => pci_req_o, + pci_req_oe_o => pci_req_oe_o, + pci_gnt_i => PCI_GNTn, + pci_frame_i => PCI_FRAMEn, + pci_frame_o => pci_frame_o, + pci_frame_oe_o => pci_frame_oe_o, + pci_irdy_oe_o => pci_irdy_oe_o, + pci_devsel_oe_o => pci_devsel_oe_o, + pci_trdy_oe_o => pci_trdy_oe_o, + pci_stop_oe_o => pci_stop_oe_o, + pci_ad_oe_o => pci_ad_oe_o, + pci_cbe_oe_o => pci_cbe_oe_o, + pci_irdy_i => PCI_IRDYn, + pci_irdy_o => pci_irdy_o, + pci_idsel_i => PCI_IDSEL, + pci_devsel_i => PCI_DEVSELn, + pci_devsel_o => pci_devsel_o, + pci_trdy_i => PCI_TRDYn, + pci_trdy_o => pci_trdy_o, + pci_stop_i => PCI_STOPn, + pci_stop_o => pci_stop_o, + pci_ad_i => PCI_AD, + pci_ad_o => pci_ad_o, + pci_cbe_i => PCI_CBEn, + pci_cbe_o => pci_cbe_o, + pci_par_i => PCI_PAR, + pci_par_o => pci_par_o, + pci_par_oe_o => pci_par_oe_o, + pci_perr_i => PCI_PERRn, + pci_perr_o => pci_perr_o, + pci_perr_oe_o => pci_perr_oe_o, + pci_serr_o => pci_serr_o, + pci_serr_oe_o => pci_serr_oe_o +); + +Inst_eth_top: eth_top PORT MAP( + wb_clk_i => , + wb_rst_i => , + wb_dat_i => , + wb_dat_o => , + wb_adr_i => , + wb_sel_i => , + wb_we_i => , + wb_cyc_i => , + wb_stb_i => , + wb_ack_o => , + wb_err_o => , + m_wb_adr_o => , + m_wb_sel_o => , + m_wb_we_o => , + m_wb_dat_o => , + m_wb_dat_i => , + m_wb_cyc_o => , + m_wb_stb_o => , + m_wb_ack_i => , + m_wb_err_i => , + mtx_clk_pad_i => , + mtxd_pad_o => , + mtxen_pad_o => , + mtxerr_pad_o => , + mrx_clk_pad_i => , + mrxd_pad_i => , + mrxdv_pad_i => , + mrxerr_pad_i => , + mcoll_pad_i => , + mcrs_pad_i => , + mdc_pad_o => , + md_pad_i => , + md_pad_o => , + md_padoe_o => , + int_o => +); + +end architecture bla;