X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/56f1d0d6d7ce34b93faf0fe935bd215897a1c58a..bba7a6d51635a1cb7d31bdfc03b1a66ee9df336b:/dhwk/source/top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index 215b980..a79c470 100644
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -20,6 +20,10 @@ entity dhwk is
 --             SPC_RDY_IN : In    std_logic;
              TAST_RESn : In    std_logic;
              TAST_SETn : In    std_logic;
+             LED_2 : out    std_logic;
+             LED_3 : out    std_logic;
+             LED_4 : out    std_logic;
+             LED_5 : out    std_logic;
               PCI_AD : InOut std_logic_vector (31 downto 0);
              PCI_PAR : InOut std_logic;
              PCI_DEVSELn : Out   std_logic;
@@ -86,6 +90,7 @@ architecture SCHEMATIC of dhwk is
    signal SPC_RDY_IN : std_logic;
    signal SERIAL_OUT : std_logic;
    signal SPC_RDY_OUT : std_logic;
+   signal watch : std_logic;
 
    component MESS_1_TB
       Port ( DEVSELn : In    std_logic;
@@ -219,6 +224,11 @@ end component;
 begin
 	SERIAL_IN <= SERIAL_OUT;
 	SPC_RDY_IN <= SPC_RDY_OUT;
+	LED_2 <= TAST_RESn;
+	LED_3 <= TAST_SETn;
+	LED_4 <= '0';
+	LED_5 <= not watch;
+	PCI_INTAn <= watch;
 
    I19 : MESS_1_TB
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
@@ -239,7 +249,7 @@ begin
                  READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
                  TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
                  TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
-                 INTAn=>INTAn, PCI_INTAn=>PCI_INTAn );
+                 INTAn=>INTAn, PCI_INTAn=>watch);
    I14 : FIFO_CONTROL
       Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
                  FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,