X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/696ded12bcd3df47aeefae2c685029a799d84abd..0b6ed0d89260ade25dc0c2dc9fb8aa154fabd6a1:/dhwk/source/PAR_SER_CON.vhd diff --git a/dhwk/source/PAR_SER_CON.vhd b/dhwk/source/PAR_SER_CON.vhd index 2544f68..7f569e2 100644 --- a/dhwk/source/PAR_SER_CON.vhd +++ b/dhwk/source/PAR_SER_CON.vhd @@ -1,123 +1,123 @@ --- $Id: PAR_SER_CON.vhd,v 1.3 2007-03-11 08:04:56 sithglan Exp $ +-- $Id: PAR_SER_CON.vhd,v 1.4 2007-03-11 08:44:31 sithglan Exp $ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity PAR_SER_CON is - port - ( - PCI_CLOCK :in std_logic; - RESET :in std_logic; - PSC_ENABLE :in std_logic; -- Parallel Serial Converter Enable - SYNC_S_FIFO_EFn :in std_logic; -- Empty Flag (low active) - SPC_RDY_IN :in std_logic; -- Ready to receive data - PAR_IN :in std_logic_vector(7 downto 0); - SER_OUT :out std_logic; -- Serial Output - S_FIFO_READn :out std_logic -- FIFO Read (low active) - ); + port + ( + PCI_CLOCK :in std_logic; + RESET :in std_logic; + PSC_ENABLE :in std_logic; -- Parallel Serial Converter Enable + SYNC_S_FIFO_EFn :in std_logic; -- Empty Flag (low active) + SPC_RDY_IN :in std_logic; -- Ready to receive data + PAR_IN :in std_logic_vector(7 downto 0); + SER_OUT :out std_logic; -- Serial Output + S_FIFO_READn :out std_logic -- FIFO Read (low active) + ); end entity PAR_SER_CON ; architecture PAR_SER_CON_DESIGN of PAR_SER_CON is -constant STATE_END :std_logic_vector(3 downto 0) := "0001"; -constant STATE_SEND :std_logic_vector(3 downto 0) := "0010"; -constant STATE_SEND_BIT_0 :std_logic_vector(3 downto 0) := "0011"; -constant STATE_SEND_BIT_1 :std_logic_vector(3 downto 0) := "0100"; -constant STATE_SEND_BIT_2 :std_logic_vector(3 downto 0) := "0101"; -constant STATE_SEND_BIT_3 :std_logic_vector(3 downto 0) := "0110"; -constant STATE_SEND_BIT_4 :std_logic_vector(3 downto 0) := "0111"; -constant STATE_SEND_BIT_5 :std_logic_vector(3 downto 0) := "1000"; -constant STATE_SEND_BIT_6 :std_logic_vector(3 downto 0) := "1001"; -constant STATE_SEND_BIT_7 :std_logic_vector(3 downto 0) := "1010"; - -signal COUNT :std_logic_vector (3 downto 0); -signal STATE :std_logic_vector (3 downto 0); -signal DATUM :std_logic_vector (7 downto 0); -signal SYNC :std_logic; -- make SPC_RDY_IN stable - -attribute syn_state_machine:boolean; -attribute syn_state_machine of STATE: signal is false; -attribute syn_state_machine of COUNT: signal is false; + constant STATE_END :std_logic_vector(3 downto 0) := "0001"; + constant STATE_SEND :std_logic_vector(3 downto 0) := "0010"; + constant STATE_SEND_BIT_0 :std_logic_vector(3 downto 0) := "0011"; + constant STATE_SEND_BIT_1 :std_logic_vector(3 downto 0) := "0100"; + constant STATE_SEND_BIT_2 :std_logic_vector(3 downto 0) := "0101"; + constant STATE_SEND_BIT_3 :std_logic_vector(3 downto 0) := "0110"; + constant STATE_SEND_BIT_4 :std_logic_vector(3 downto 0) := "0111"; + constant STATE_SEND_BIT_5 :std_logic_vector(3 downto 0) := "1000"; + constant STATE_SEND_BIT_6 :std_logic_vector(3 downto 0) := "1001"; + constant STATE_SEND_BIT_7 :std_logic_vector(3 downto 0) := "1010"; + + signal COUNT :std_logic_vector (3 downto 0); + signal STATE :std_logic_vector (3 downto 0); + signal DATUM :std_logic_vector (7 downto 0); + signal SYNC :std_logic; -- make SPC_RDY_IN stable + + attribute syn_state_machine:boolean; + attribute syn_state_machine of STATE: signal is false; + attribute syn_state_machine of COUNT: signal is false; begin -process(PCI_CLOCK) -begin - if (PCI_CLOCK'event and PCI_CLOCK = '1') then - if ("0000" < COUNT) then - COUNT <= COUNT - 1; - end if; - - if (RESET = '1') then - STATE <= STATE_SEND; - COUNT <= "0000"; - SER_OUT <= '0'; - S_FIFO_READn <= '1'; - - elsif (PSC_ENABLE = '1') then - if (COUNT = "0000") then - COUNT <= "0011"; - case STATE is - when STATE_SEND => - if(SYNC = '1' and SYNC_S_FIFO_EFn = '1') then - SER_OUT <= '1'; - S_FIFO_READn <= '0'; - STATE <= STATE_SEND_BIT_0; - end if; - - when STATE_SEND_BIT_0 => + process(PCI_CLOCK) + begin + if (PCI_CLOCK'event and PCI_CLOCK = '1') then + if ("0000" < COUNT) then + COUNT <= COUNT - 1; + end if; + + if (RESET = '1') then + STATE <= STATE_SEND; + COUNT <= "0000"; + SER_OUT <= '0'; + S_FIFO_READn <= '1'; + + elsif (PSC_ENABLE = '1') then + if (COUNT = "0000") then + COUNT <= "0011"; + case STATE is + when STATE_SEND => + if(SYNC = '1' and SYNC_S_FIFO_EFn = '1') then + SER_OUT <= '1'; + S_FIFO_READn <= '0'; + STATE <= STATE_SEND_BIT_0; + end if; + + when STATE_SEND_BIT_0 => DATUM <= PAR_IN; S_FIFO_READn <= '1'; SER_OUT <= PAR_IN(0); STATE <= STATE_SEND_BIT_1; - - when STATE_SEND_BIT_1 => - SER_OUT <= DATUM(1); - STATE <= STATE_SEND_BIT_2; - - when STATE_SEND_BIT_2 => - SER_OUT <= DATUM(2); - STATE <= STATE_SEND_BIT_3; - - when STATE_SEND_BIT_3 => - SER_OUT <= DATUM(3); - STATE <= STATE_SEND_BIT_4; - - when STATE_SEND_BIT_4 => - SER_OUT <= DATUM(4); - STATE <= STATE_SEND_BIT_5; - - when STATE_SEND_BIT_5 => - SER_OUT <= DATUM(5); - STATE <= STATE_SEND_BIT_6; - - when STATE_SEND_BIT_6 => - SER_OUT <= DATUM(6); - STATE <= STATE_SEND_BIT_7; - - when STATE_SEND_BIT_7 => - SER_OUT <= DATUM(7); - STATE <= STATE_END; - - when STATE_END => - SER_OUT <= '0'; - STATE <= STATE_SEND; - - when others => STATE <= STATE_END; - end case; - else - S_FIFO_READn <= '1'; - end if; -- COUNT - end if; -- RESET ... / PSC_ENABLE ... - end if; -- PCI_CLOCK ... -end process; - -process(PCI_CLOCK) -begin - if (PCI_CLOCK'event and PCI_CLOCK = '1') then - SYNC <= SPC_RDY_IN; - end if; -end process; + when STATE_SEND_BIT_1 => + SER_OUT <= DATUM(1); + STATE <= STATE_SEND_BIT_2; + + when STATE_SEND_BIT_2 => + SER_OUT <= DATUM(2); + STATE <= STATE_SEND_BIT_3; + + when STATE_SEND_BIT_3 => + SER_OUT <= DATUM(3); + STATE <= STATE_SEND_BIT_4; + + when STATE_SEND_BIT_4 => + SER_OUT <= DATUM(4); + STATE <= STATE_SEND_BIT_5; + + when STATE_SEND_BIT_5 => + SER_OUT <= DATUM(5); + STATE <= STATE_SEND_BIT_6; + + when STATE_SEND_BIT_6 => + SER_OUT <= DATUM(6); + STATE <= STATE_SEND_BIT_7; + + when STATE_SEND_BIT_7 => + SER_OUT <= DATUM(7); + STATE <= STATE_END; + + when STATE_END => + SER_OUT <= '0'; + STATE <= STATE_SEND; + + when others => STATE <= STATE_END; + end case; + + else + S_FIFO_READn <= '1'; + end if; -- COUNT + end if; -- RESET ... / PSC_ENABLE ... + end if; -- PCI_CLOCK ... + end process; + + process(PCI_CLOCK) + begin + if (PCI_CLOCK'event and PCI_CLOCK = '1') then + SYNC <= SPC_RDY_IN; + end if; + end process; end architecture PAR_SER_CON_DESIGN;