X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/696ded12bcd3df47aeefae2c685029a799d84abd..0b6ed0d89260ade25dc0c2dc9fb8aa154fabd6a1:/dhwk/source/parity_out.vhd

diff --git a/dhwk/source/parity_out.vhd b/dhwk/source/parity_out.vhd
index 55ba210..c8ecfa7 100644
--- a/dhwk/source/parity_out.vhd
+++ b/dhwk/source/parity_out.vhd
@@ -7,60 +7,54 @@ library ieee;
 use ieee.std_logic_1164.all;
 
 entity PARITY_OUT is
-	port(
-		PCI_CLOCK		:in		std_logic;
-		PCI_RSTn		:in		std_logic;
-		PAR_IN			:in		std_logic_vector ( 2 downto 0);	
-		PAR_REG			:in		std_logic;
-		SERR_CHECK	:in		std_logic;	
-		PERR_CHECK	:in		std_logic;
-		OE_PCI_PAR	:in		std_logic;
-		OE_PCI_PERR	:in		std_logic;
-		PA_ER_RE		:in		std_logic;
-		SERR_ENA		:in		std_logic;
-		PCI_PAR_IN	:in		std_logic;
-		PERR				:out	std_logic;
-		SERR				:out	std_logic;
-		PCI_PERRn		:out	std_logic;	--	s/t/s
-		PCI_SERRn		:out	std_logic;	--	o/d
-		PCI_PAR			:out	std_logic		--	t/s
-		);
-end entity PARITY_OUT; 
+        port(
+                    PCI_CLOCK :in std_logic;
+                    PCI_RSTn :in std_logic;
+                    PAR_IN :in std_logic_vector ( 2 downto 0);
+                    PAR_REG :in std_logic;
+                    SERR_CHECK :in std_logic;
+                    PERR_CHECK :in std_logic;
+                    OE_PCI_PAR :in std_logic;
+                    OE_PCI_PERR :in std_logic;
+                    PA_ER_RE :in std_logic;
+                    SERR_ENA :in std_logic;
+                    PCI_PAR_IN :in std_logic;
+                    PERR :out std_logic;
+                    SERR :out std_logic;
+                    PCI_PERRn :out std_logic; -- s/t/s
+                    PCI_SERRn :out std_logic; -- o/d
+                    PCI_PAR :out std_logic -- t/s
+            );
+end entity PARITY_OUT;
 
 architecture PARITY_OUT_DESIGN of PARITY_OUT is
 
-	signal PAR			:std_logic;
-	signal PAR_FF		:std_logic;
-	signal SERR_FF	:std_logic;
-	signal PERR_FF	:std_logic;
-  
-begin
-
-	PAR		<= ( PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) ); 
+        signal PAR :std_logic;
+        signal PAR_FF :std_logic;
+        signal SERR_FF :std_logic;
+        signal PERR_FF :std_logic;
 
-	process (PCI_CLOCK, PCI_RSTn) 
-	begin
-		if	PCI_RSTn = '0'	then	PAR_FF	<= '0';
-															PERR_FF	<= '0';
-															SERR_FF	<= '0'; 
+begin
 
-		elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+        PAR <= ( PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) );
 
-			PAR_FF	<=	PAR;
-			SERR_FF	<=	((PCI_PAR_IN xor PAR) and SERR_CHECK) and PA_ER_RE and SERR_ENA and (not SERR_FF);   
-			PERR_FF	<=	((PCI_PAR_IN xor PAR) and PERR_CHECK) and (not PERR_FF);  
+        process (PCI_CLOCK, PCI_RSTn)
+        begin
+        if PCI_RSTn = '0' then PAR_FF <= '0';
+                PERR_FF <= '0';
+                SERR_FF <= '0';
 
-		end if;
-	end process; 
+        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                SERR_FF <= ((PCI_PAR_IN xor PAR) and SERR_CHECK) and PA_ER_RE and SERR_ENA and (not SERR_FF);
+                PERR_FF <= ((PCI_PAR_IN xor PAR) and PERR_CHECK) and (not PERR_FF);
+        end if;
+end process;
 
-	SERR			<=  SERR_FF;
-	PERR			<=  PERR_FF;
+SERR <= SERR_FF;
+PERR <= PERR_FF;
 
-	PCI_PAR		<= PAR_FF				when	OE_PCI_PAR	= '1' else 'Z' ; 
-	PCI_SERRn	<= '0'					when	SERR_FF			= '1' else 'Z' ;
-	PCI_PERRn	<= not PERR_FF	when	OE_PCI_PERR	= '1' and PA_ER_RE = '1' else 'Z' ;
+PCI_PAR <= PAR_FF when OE_PCI_PAR = '1' else 'Z';
+PCI_SERRn <= '0' when SERR_FF = '1' else 'Z';
+PCI_PERRn <= not PERR_FF when OE_PCI_PERR = '1' and PA_ER_RE = '1' else 'Z';
 
 end architecture PARITY_OUT_DESIGN;
-
-
-