X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/696ded12bcd3df47aeefae2c685029a799d84abd..0b6ed0d89260ade25dc0c2dc9fb8aa154fabd6a1:/dhwk/source/verg_8.vhd

diff --git a/dhwk/source/verg_8.vhd b/dhwk/source/verg_8.vhd
index 618a0cc..ea7a499 100644
--- a/dhwk/source/verg_8.vhd
+++ b/dhwk/source/verg_8.vhd
@@ -7,22 +7,21 @@ library ieee;
 use ieee.std_logic_1164.all;
 
 entity VERG_8 is
-	port
-	(
-	GLEICH			:in		std_logic_vector(7 downto 0);
-	GLEICH_OUT	:out	std_logic
-	);
+        port
+        (
+                GLEICH :in std_logic_vector(7 downto 0);
+                GLEICH_OUT :out std_logic
+        );
 
-end entity VERG_8 ;
+end entity VERG_8;
 
 architecture VERG_8_DESIGN of VERG_8 is
- 
 
 begin
 
---	GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte
+ -- GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte
 
---	GLEICH_OUT	<=	'1'	when	GLEICH(7 downto 0)	=	"11111111"	else	'0';    
-		GLEICH_OUT	<=	'1'	when	GLEICH(7 downto 1)	=	"1111111"		else	'0'; 
- 
-end architecture VERG_8_DESIGN ;
+ -- GLEICH_OUT <= '1' when GLEICH(7 downto 0) = "11111111" else '0';
+    GLEICH_OUT <= '1' when GLEICH(7 downto 1) = "1111111" else '0';
+
+end architecture VERG_8_DESIGN;