X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/696ded12bcd3df47aeefae2c685029a799d84abd..2612d712ff5ef3f17a3d55ae22c71a1913fa1fee:/dhwk/source/Verg_2.vhd

diff --git a/dhwk/source/Verg_2.vhd b/dhwk/source/Verg_2.vhd
index 94aa714..bbea0ea 100644
--- a/dhwk/source/Verg_2.vhd
+++ b/dhwk/source/Verg_2.vhd
@@ -3,29 +3,31 @@
 -- 23.08.2006
 -- File: VERG_2.VHD
 
-library ieee ;
-use ieee.std_logic_1164.all ;
-
-entity	VERG_2	is
-	port
-	(
- 	IN_A		:in		std_logic_vector(1 downto 0);
- 	IN_B		:in		std_logic_vector(1 downto 0);
-	GLEICH	:out	std_logic
-	);
-end entity VERG_2 ;
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity VERG_2 is
+        port
+        (
+                IN_A :in std_logic_vector(1 downto 0);
+                IN_B :in std_logic_vector(1 downto 0);
+                GLEICH :out std_logic
+        );
+end entity VERG_2;
 
 architecture VERG_2_DESIGN of VERG_2 is
 
 begin
 
-	process (IN_A,IN_B) 
-	begin 
+        process (IN_A,IN_B)
+        begin
 
-		if			IN_A	=	IN_B	then	GLEICH	<=	'1';
-			else											GLEICH	<=	'0';   
-		end if;
+        if IN_A = IN_B then
+                GLEICH <= '1';
+        else
+                GLEICH <= '0';
+        end if;
 
-	end process;
+end process;
 
-end architecture VERG_2_DESIGN ;
+end architecture VERG_2_DESIGN;