X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/696ded12bcd3df47aeefae2c685029a799d84abd..2612d712ff5ef3f17a3d55ae22c71a1913fa1fee:/dhwk/source/ven_rev_id.vhd

diff --git a/dhwk/source/ven_rev_id.vhd b/dhwk/source/ven_rev_id.vhd
index 669264e..ad90461 100644
--- a/dhwk/source/ven_rev_id.vhd
+++ b/dhwk/source/ven_rev_id.vhd
@@ -7,18 +7,18 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 
 entity VEN_REV_ID is
-	port
-	(
-	VEN_ID	:out	std_logic_vector(15 downto 0);
-	REV_ID	:out	std_logic_vector( 7 downto 0)
-	);
+        port
+        (
+                VEN_ID :out std_logic_vector(15 downto 0);
+                REV_ID :out std_logic_vector( 7 downto 0)
+        );
 end entity VEN_REV_ID;
 
 architecture VEN_REV_ID_DESIGN of VEN_REV_ID is
 
 begin
 
-	VEN_ID	<= X"2222";
-	REV_ID	<= X"01";
+        VEN_ID <= X"2222";
+        REV_ID <= X"01";
 
 end architecture VEN_REV_ID_DESIGN;