X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/6d5ab91b9b53062d8fcef1cfd76b2e6612690804..e00b64cc5780386174db7506cad5bccee09087b0:/dhwk/source/pci/config_space_header.vhd?ds=sidebyside

diff --git a/dhwk/source/pci/config_space_header.vhd b/dhwk/source/pci/config_space_header.vhd
index 9114785..15db761 100644
--- a/dhwk/source/pci/config_space_header.vhd
+++ b/dhwk/source/pci/config_space_header.vhd
@@ -27,15 +27,6 @@ end CONFIG_SPACE_HEADER;
 
 architecture SCHEMATIC of CONFIG_SPACE_HEADER is
 
-        constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";
-        --other comm. device
-        constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000";
-
-        signal CONF_MAX_LAT :std_logic_vector (31 downto 24);
-        signal CONF_MIN_GNT :std_logic_vector (23 downto 16);
-        signal CONF_INT_PIN :std_logic_vector (15 downto 8);
-        signal CONF_INT_LINE :std_logic_vector ( 7 downto 0);
-
         SIGNAL gnd : std_logic := '0';
         SIGNAL vcc : std_logic := '1';
 
@@ -75,6 +66,15 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
                        CONF_WR_3CH : Out std_logic );
         end component;
 
+        component CONFIG_3CH
+                Port ( AD_REG : In std_logic_vector (31 downto 0);
+                       CBE_REGn : In std_logic_vector (3 downto 0);
+                       CONF_WR_3CH : In std_logic;
+                       PCI_CLOCK : In std_logic;
+                       PCI_RSTn : In std_logic;
+                       CONF_DATA_3CH : Out std_logic_vector (31 downto 0) );
+        end component;
+
         component CONFIG_10H
                 Port ( AD_REG : In std_logic_vector (31 downto 0);
                        CBE_REGn : In std_logic_vector (3 downto 0);
@@ -84,6 +84,16 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
                        CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
         end component;
 
+        component CONFIG_08H
+                Port ( REVISION_ID : In std_logic_vector (7 downto 0);
+                       CONF_DATA_08H : Out std_logic_vector (31 downto 0) );
+        end component;
+
+        component CONFIG_00H
+                Port ( VENDOR_ID : In std_logic_vector (15 downto 0);
+                       CONF_DATA_00H : Out std_logic_vector (31 downto 0) );
+        end component;
+
         component CONFIG_04H
                 Port ( AD_REG : In std_logic_vector (31 downto 0);
                        CBE_REGn : In std_logic_vector (3 downto 0);
@@ -96,22 +106,10 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
         end component;
 
 begin
-        CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
-        CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
 
         CONF_DATA_04H <= CONF_DATA_04H_DUMMY;
         CONF_DATA_10H <= CONF_DATA_10H_DUMMY;
 
-        CONF_MAX_LAT <= X"00";
-        CONF_MIN_GNT <= X"00";
-        -- CONF_INT_PIN <= X"00"; -- Interrupt -
-        CONF_INT_PIN <= X"01"; -- Interrupt A
-        -- CONF_INT_PIN <= X"02"; -- Interrupt B
-        -- CONF_INT_PIN <= X"03"; -- Interrupt C
-        -- CONF_INT_PIN <= X"04"; -- Interrupt D
-        -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert
-        CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;
-
         I10 : CONFIG_MUX_0
         Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),
         CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),
@@ -129,12 +127,24 @@ begin
                    CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
                    TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
                    CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );
+        I6 : CONFIG_3CH
+        Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+        CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+        CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,
+        PCI_RSTn=>PCI_RSTn,
+        CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );
         I5 : CONFIG_10H
         Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
         CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
         CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,
         PCI_RSTn=>PCI_RSTn,
         CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );
+        I4 : CONFIG_08H
+        Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),
+        CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );
+        I3 : CONFIG_00H
+        Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
+        CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) );
         I2 : CONFIG_04H
         Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
         CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
@@ -142,15 +152,4 @@ begin
         PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,
         CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );
 
-        process (PCI_CLOCK,PCI_RSTn)
-        begin
-                if PCI_RSTn = '0' then
-                        CONF_INT_LINE <= (others => '0');
-
-                elsif (rising_edge(PCI_CLOCK)) then
-                        if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then
-                                CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
-                        end if;
-                end if;
-        end process;
 end SCHEMATIC;