X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/6f242c755ee8ce5544f230c2390f9cc684685f96..2612d712ff5ef3f17a3d55ae22c71a1913fa1fee:/dhwk/source/pci_interface.vhd diff --git a/dhwk/source/pci_interface.vhd b/dhwk/source/pci_interface.vhd index cbca14d..722cce6 100644 --- a/dhwk/source/pci_interface.vhd +++ b/dhwk/source/pci_interface.vhd @@ -1,7 +1,5 @@ -- VHDL model created from schematic pci_interface.sch -- Jan 09 09:34:13 2007 - - LIBRARY ieee; USE ieee.std_logic_1164.ALL; @@ -9,219 +7,219 @@ USE ieee.numeric_std.ALL; entity PCI_INTERFACE is - Port ( PCI_CBEn : In std_logic_vector (3 downto 0); - PCI_CLOCK : In std_logic; - PCI_FRAMEn : In std_logic; - PCI_IDSEL : In std_logic; - PCI_IRDYn : In std_logic; - PCI_RSTn : In std_logic; - READ_FIFO : In std_logic; - REVISON_ID : In std_logic_vector (7 downto 0); - USER_DATA_OUT : In std_logic_vector (31 downto 0); - VENDOR_ID : In std_logic_vector (15 downto 0); - PCI_AD : InOut std_logic_vector (31 downto 0); - PCI_PAR : InOut std_logic; - AD_REG : Out std_logic_vector (31 downto 0); - ADDR_REG : Out std_logic_vector (31 downto 0); - CBE_REGn : Out std_logic_vector (3 downto 0); - DEVSELn : Out std_logic; - FIFO_RDn : Out std_logic; - IO_WR_COM : Out std_logic; - IRDY_REGn : Out std_logic; - PCI_DEVSELn : Out std_logic; - PCI_PERRn : Out std_logic; - PCI_SERRn : Out std_logic; - PCI_STOPn : Out std_logic; - PCI_TRDYn : Out std_logic; - READ_SEL : Out std_logic_vector (1 downto 0); - TRDYn : Out std_logic ); + Port ( PCI_CBEn : In std_logic_vector (3 downto 0); + PCI_CLOCK : In std_logic; + PCI_FRAMEn : In std_logic; + PCI_IDSEL : In std_logic; + PCI_IRDYn : In std_logic; + PCI_RSTn : In std_logic; + READ_FIFO : In std_logic; + REVISON_ID : In std_logic_vector (7 downto 0); + USER_DATA_OUT : In std_logic_vector (31 downto 0); + VENDOR_ID : In std_logic_vector (15 downto 0); + PCI_AD : InOut std_logic_vector (31 downto 0); + PCI_PAR : InOut std_logic; + AD_REG : Out std_logic_vector (31 downto 0); + ADDR_REG : Out std_logic_vector (31 downto 0); + CBE_REGn : Out std_logic_vector (3 downto 0); + DEVSELn : Out std_logic; + FIFO_RDn : Out std_logic; + IO_WR_COM : Out std_logic; + IRDY_REGn : Out std_logic; + PCI_DEVSELn : Out std_logic; + PCI_PERRn : Out std_logic; + PCI_SERRn : Out std_logic; + PCI_STOPn : Out std_logic; + PCI_TRDYn : Out std_logic; + READ_SEL : Out std_logic_vector (1 downto 0); + TRDYn : Out std_logic ); end PCI_INTERFACE; architecture SCHEMATIC of PCI_INTERFACE is - SIGNAL gnd : std_logic := '0'; - SIGNAL vcc : std_logic := '1'; - - signal IRDY_REGn_DUMMY : std_logic; - signal PAR_REG : std_logic; - signal PERR : std_logic; - signal SERR : std_logic; - signal CF_RD_COM : std_logic; - signal CF_WR_COM : std_logic; - signal LAR : std_logic; - signal MY_ADDR : std_logic; - signal SERR_CHECK : std_logic; - signal IDSEL_REG : std_logic; - signal FRAME_REGn : std_logic; - signal PERR_CHECK : std_logic; - signal OE_PCI_PAR : std_logic; - signal OE_PCI_PERR : std_logic; - signal TRDYn_DUMMY : std_logic; - signal CONF_DATA_10H : std_logic_vector (31 downto 0); - signal CONF_DATA_04H : std_logic_vector (31 downto 0); - signal CONF_DATA : std_logic_vector (31 downto 0); - signal READ_SEL_DUMMY : std_logic_vector (1 downto 0); - signal CBE_REGn_DUMMY : std_logic_vector (3 downto 0); - signal AD_REG_DUMMY : std_logic_vector (31 downto 0); - signal ADDR_REG_DUMMY : std_logic_vector (31 downto 0); - - component STEUERUNG - Port ( AD_REG : In std_logic_vector (31 downto 0); - CBE_REGn : In std_logic_vector (3 downto 0); - FRAME_REGn : In std_logic; - IDSEL_REG : In std_logic; - IO_SPACE : In std_logic; - MY_ADDR : In std_logic; - PCI_CLOCK : In std_logic; - PCI_RSTn : In std_logic; - READ_FIFO : In std_logic; - CF_RD_COM : Out std_logic; - CF_WR_COM : Out std_logic; - DEVSELn : Out std_logic; - FIFO_RDn : Out std_logic; - IO_RD_COM : Out std_logic; - IO_WR_COM : Out std_logic; - LAR : Out std_logic; - OE_PCI_PAR : Out std_logic; - OE_PCI_PERR : Out std_logic; - PCI_DEVSELn : Out std_logic; - PCI_STOPn : Out std_logic; - PCI_TRDYn : Out std_logic; - PERR_CHECK : Out std_logic; - READ : Out std_logic; - SERR_CHECK : Out std_logic; - TRDYn : Out std_logic ); - end component; - - component PARITY - Port ( OE_PCI_PAR : In std_logic; - OE_PCI_PERR : In std_logic; - PA_ER_RE : In std_logic; - PAR_IN : In std_logic_vector (35 downto 0); - PAR_REG : In std_logic; - PCI_CLOCK : In std_logic; - PCI_RSTn : In std_logic; - PERR_CHECK : In std_logic; - SERR_CHECK : In std_logic; - SERR_ENA : In std_logic; - PCI_PAR : InOut std_logic; - PCI_PERRn : Out std_logic; - PCI_SERRn : Out std_logic; - PERR : Out std_logic; - SERR : Out std_logic ); - end component; - - component VERGLEICH - Port ( IN_A : In std_logic_vector (31 downto 0); - IN_B : In std_logic_vector (31 downto 0); - GLEICH_OUT : Out std_logic ); - end component; - - component IO_MUX_REG - Port ( CONFIG_DATA : In std_logic_vector (31 downto 0); - LOAD_ADDR_REG : In std_logic; - PCI_CBEn : In std_logic_vector (3 downto 0); - PCI_CLOCK : In std_logic; - PCI_FRAMEn : In std_logic; - PCI_IDSEL : In std_logic; - PCI_IRDYn : In std_logic; - PCI_PAR : In std_logic; - PCI_RSTn : In std_logic; - READ_SEL : In std_logic_vector (1 downto 0); - USER_DATA : In std_logic_vector (31 downto 0); - PCI_AD : InOut std_logic_vector (31 downto 0); - AD_REG : Out std_logic_vector (31 downto 0); - ADDR_REG : Out std_logic_vector (31 downto 0); - CBE_REGn : Out std_logic_vector (3 downto 0); - FRAME_REGn : Out std_logic; - IDSEL_REG : Out std_logic; - IRDY_REGn : Out std_logic; - PAR_REG : Out std_logic ); - end component; - - component CONFIG_SPACE_HEADER - Port ( AD_REG : In std_logic_vector (31 downto 0); - ADDR_REG : In std_logic_vector (31 downto 0); - CBE_REGn : In std_logic_vector (3 downto 0); - CF_RD_COM : In std_logic; - CF_WR_COM : In std_logic; - IRDY_REGn : In std_logic; - PCI_CLOCK : In std_logic; - PCI_RSTn : In std_logic; - PERR : In std_logic; - REVISION_ID : In std_logic_vector (7 downto 0); - SERR : In std_logic; - TRDYn : In std_logic; - VENDOR_ID : In std_logic_vector (15 downto 0); - CONF_DATA : Out std_logic_vector (31 downto 0); - CONF_DATA_04H : Out std_logic_vector (31 downto 0); - CONF_DATA_10H : Out std_logic_vector (31 downto 0) ); - end component; + SIGNAL gnd : std_logic := '0'; + SIGNAL vcc : std_logic := '1'; + + signal IRDY_REGn_DUMMY : std_logic; + signal PAR_REG : std_logic; + signal PERR : std_logic; + signal SERR : std_logic; + signal CF_RD_COM : std_logic; + signal CF_WR_COM : std_logic; + signal LAR : std_logic; + signal MY_ADDR : std_logic; + signal SERR_CHECK : std_logic; + signal IDSEL_REG : std_logic; + signal FRAME_REGn : std_logic; + signal PERR_CHECK : std_logic; + signal OE_PCI_PAR : std_logic; + signal OE_PCI_PERR : std_logic; + signal TRDYn_DUMMY : std_logic; + signal CONF_DATA_10H : std_logic_vector (31 downto 0); + signal CONF_DATA_04H : std_logic_vector (31 downto 0); + signal CONF_DATA : std_logic_vector (31 downto 0); + signal READ_SEL_DUMMY : std_logic_vector (1 downto 0); + signal CBE_REGn_DUMMY : std_logic_vector (3 downto 0); + signal AD_REG_DUMMY : std_logic_vector (31 downto 0); + signal ADDR_REG_DUMMY : std_logic_vector (31 downto 0); + + component STEUERUNG + Port ( AD_REG : In std_logic_vector (31 downto 0); + CBE_REGn : In std_logic_vector (3 downto 0); + FRAME_REGn : In std_logic; + IDSEL_REG : In std_logic; + IO_SPACE : In std_logic; + MY_ADDR : In std_logic; + PCI_CLOCK : In std_logic; + PCI_RSTn : In std_logic; + READ_FIFO : In std_logic; + CF_RD_COM : Out std_logic; + CF_WR_COM : Out std_logic; + DEVSELn : Out std_logic; + FIFO_RDn : Out std_logic; + IO_RD_COM : Out std_logic; + IO_WR_COM : Out std_logic; + LAR : Out std_logic; + OE_PCI_PAR : Out std_logic; + OE_PCI_PERR : Out std_logic; + PCI_DEVSELn : Out std_logic; + PCI_STOPn : Out std_logic; + PCI_TRDYn : Out std_logic; + PERR_CHECK : Out std_logic; + READ : Out std_logic; + SERR_CHECK : Out std_logic; + TRDYn : Out std_logic ); + end component; + + component PARITY + Port ( OE_PCI_PAR : In std_logic; + OE_PCI_PERR : In std_logic; + PA_ER_RE : In std_logic; + PAR_IN : In std_logic_vector (35 downto 0); + PAR_REG : In std_logic; + PCI_CLOCK : In std_logic; + PCI_RSTn : In std_logic; + PERR_CHECK : In std_logic; + SERR_CHECK : In std_logic; + SERR_ENA : In std_logic; + PCI_PAR : InOut std_logic; + PCI_PERRn : Out std_logic; + PCI_SERRn : Out std_logic; + PERR : Out std_logic; + SERR : Out std_logic ); + end component; + + component VERGLEICH + Port ( IN_A : In std_logic_vector (31 downto 0); + IN_B : In std_logic_vector (31 downto 0); + GLEICH_OUT : Out std_logic ); + end component; + + component IO_MUX_REG + Port ( CONFIG_DATA : In std_logic_vector (31 downto 0); + LOAD_ADDR_REG : In std_logic; + PCI_CBEn : In std_logic_vector (3 downto 0); + PCI_CLOCK : In std_logic; + PCI_FRAMEn : In std_logic; + PCI_IDSEL : In std_logic; + PCI_IRDYn : In std_logic; + PCI_PAR : In std_logic; + PCI_RSTn : In std_logic; + READ_SEL : In std_logic_vector (1 downto 0); + USER_DATA : In std_logic_vector (31 downto 0); + PCI_AD : InOut std_logic_vector (31 downto 0); + AD_REG : Out std_logic_vector (31 downto 0); + ADDR_REG : Out std_logic_vector (31 downto 0); + CBE_REGn : Out std_logic_vector (3 downto 0); + FRAME_REGn : Out std_logic; + IDSEL_REG : Out std_logic; + IRDY_REGn : Out std_logic; + PAR_REG : Out std_logic ); + end component; + + component CONFIG_SPACE_HEADER + Port ( AD_REG : In std_logic_vector (31 downto 0); + ADDR_REG : In std_logic_vector (31 downto 0); + CBE_REGn : In std_logic_vector (3 downto 0); + CF_RD_COM : In std_logic; + CF_WR_COM : In std_logic; + IRDY_REGn : In std_logic; + PCI_CLOCK : In std_logic; + PCI_RSTn : In std_logic; + PERR : In std_logic; + REVISION_ID : In std_logic_vector (7 downto 0); + SERR : In std_logic; + TRDYn : In std_logic; + VENDOR_ID : In std_logic_vector (15 downto 0); + CONF_DATA : Out std_logic_vector (31 downto 0); + CONF_DATA_04H : Out std_logic_vector (31 downto 0); + CONF_DATA_10H : Out std_logic_vector (31 downto 0) ); + end component; begin - ADDR_REG <= ADDR_REG_DUMMY; - AD_REG <= AD_REG_DUMMY; - CBE_REGn <= CBE_REGn_DUMMY; - READ_SEL <= READ_SEL_DUMMY; - TRDYn <= TRDYn_DUMMY; - IRDY_REGn <= IRDY_REGn_DUMMY; - - I7 : STEUERUNG - Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0), - CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0), - FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG, - IO_SPACE=>CONF_DATA_04H(0), MY_ADDR=>MY_ADDR, - PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn, - READ_FIFO=>READ_FIFO, CF_RD_COM=>CF_RD_COM, - CF_WR_COM=>CF_WR_COM, DEVSELn=>DEVSELn, - FIFO_RDn=>FIFO_RDn, IO_RD_COM=>READ_SEL_DUMMY(0), - IO_WR_COM=>IO_WR_COM, LAR=>LAR, OE_PCI_PAR=>OE_PCI_PAR, - OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn, - PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn, - PERR_CHECK=>PERR_CHECK, READ=>READ_SEL_DUMMY(1), - SERR_CHECK=>SERR_CHECK, TRDYn=>TRDYn_DUMMY ); - I5 : PARITY - Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR, - PA_ER_RE=>CONF_DATA_04H(6), - PAR_IN(31 downto 0)=>AD_REG_DUMMY(31 downto 0), - PAR_IN(35 downto 32)=>CBE_REGn_DUMMY(3 downto 0), - PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK, - PCI_RSTn=>PCI_RSTn, PERR_CHECK=>PERR_CHECK, - SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8), - PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn, - PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR ); - I4 : VERGLEICH - Port Map ( IN_A(31 downto 0)=>CONF_DATA_10H(31 downto 0), - IN_B(31 downto 0)=>AD_REG_DUMMY(31 downto 0), - GLEICH_OUT=>MY_ADDR ); - I2 : IO_MUX_REG - Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0), - LOAD_ADDR_REG=>LAR, - PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0), - PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn, - PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn, - PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn, - READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0), - USER_DATA(31 downto 0)=>USER_DATA_OUT(31 downto 0), - PCI_AD(31 downto 0)=>PCI_AD(31 downto 0), - AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0), - ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0), - CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0), - FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG, - IRDY_REGn=>IRDY_REGn_DUMMY, PAR_REG=>PAR_REG ); - I1 : CONFIG_SPACE_HEADER - Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0), - ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0), - CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0), - CF_RD_COM=>CF_RD_COM, CF_WR_COM=>CF_WR_COM, - IRDY_REGn=>IRDY_REGn_DUMMY, PCI_CLOCK=>PCI_CLOCK, - PCI_RSTn=>PCI_RSTn, PERR=>PERR, - REVISION_ID(7 downto 0)=>REVISON_ID(7 downto 0), - SERR=>SERR, TRDYn=>TRDYn_DUMMY, - VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0), - CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0), - CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0), - CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) ); + ADDR_REG <= ADDR_REG_DUMMY; + AD_REG <= AD_REG_DUMMY; + CBE_REGn <= CBE_REGn_DUMMY; + READ_SEL <= READ_SEL_DUMMY; + TRDYn <= TRDYn_DUMMY; + IRDY_REGn <= IRDY_REGn_DUMMY; + + I7 : STEUERUNG + Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0), + CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0), + FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG, + IO_SPACE=>CONF_DATA_04H(0), MY_ADDR=>MY_ADDR, + PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn, + READ_FIFO=>READ_FIFO, CF_RD_COM=>CF_RD_COM, + CF_WR_COM=>CF_WR_COM, DEVSELn=>DEVSELn, + FIFO_RDn=>FIFO_RDn, IO_RD_COM=>READ_SEL_DUMMY(0), + IO_WR_COM=>IO_WR_COM, LAR=>LAR, OE_PCI_PAR=>OE_PCI_PAR, + OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn, + PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn, + PERR_CHECK=>PERR_CHECK, READ=>READ_SEL_DUMMY(1), + SERR_CHECK=>SERR_CHECK, TRDYn=>TRDYn_DUMMY ); + I5 : PARITY + Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR, + PA_ER_RE=>CONF_DATA_04H(6), + PAR_IN(31 downto 0)=>AD_REG_DUMMY(31 downto 0), + PAR_IN(35 downto 32)=>CBE_REGn_DUMMY(3 downto 0), + PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK, + PCI_RSTn=>PCI_RSTn, PERR_CHECK=>PERR_CHECK, + SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8), + PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn, + PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR ); + I4 : VERGLEICH + Port Map ( IN_A(31 downto 0)=>CONF_DATA_10H(31 downto 0), + IN_B(31 downto 0)=>AD_REG_DUMMY(31 downto 0), + GLEICH_OUT=>MY_ADDR ); + I2 : IO_MUX_REG + Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0), + LOAD_ADDR_REG=>LAR, + PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0), + PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn, + PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn, + PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn, + READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0), + USER_DATA(31 downto 0)=>USER_DATA_OUT(31 downto 0), + PCI_AD(31 downto 0)=>PCI_AD(31 downto 0), + AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0), + ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0), + CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0), + FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG, + IRDY_REGn=>IRDY_REGn_DUMMY, PAR_REG=>PAR_REG ); + I1 : CONFIG_SPACE_HEADER + Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0), + ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0), + CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0), + CF_RD_COM=>CF_RD_COM, CF_WR_COM=>CF_WR_COM, + IRDY_REGn=>IRDY_REGn_DUMMY, PCI_CLOCK=>PCI_CLOCK, + PCI_RSTn=>PCI_RSTn, PERR=>PERR, + REVISION_ID(7 downto 0)=>REVISON_ID(7 downto 0), + SERR=>SERR, TRDYn=>TRDYn_DUMMY, + VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0), + CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0), + CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0), + CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) ); end SCHEMATIC;