X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/70f633de02777501eba552b2a46df48f37dab136..a93ef3acf570a7f2bd850608f286510d291a199d:/ethernet/source/top.vhd?ds=sidebyside diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd index d181c52..f7c5bd9 100644 --- a/ethernet/source/top.vhd +++ b/ethernet/source/top.vhd @@ -32,6 +32,8 @@ PORT( MD_PAD_IO : INOUT std_logic; MDC_PAD_O : OUT std_logic; + PHY_CLOCK : OUT std_logic; + LED_2 : OUT std_logic ); end ethernet; @@ -154,48 +156,28 @@ PORT( ); END COMPONENT; -COMPONENT eth_cop -PORT( - wb_clk_i : IN std_logic; - wb_rst_i : IN std_logic; - m1_wb_adr_i : IN std_logic_vector(31 downto 0); - m1_wb_sel_i : IN std_logic_vector(3 downto 0); - m1_wb_we_i : IN std_logic; - m1_wb_dat_i : IN std_logic_vector(31 downto 0); - m1_wb_cyc_i : IN std_logic; - m1_wb_stb_i : IN std_logic; - m2_wb_adr_i : IN std_logic_vector(31 downto 0); - m2_wb_sel_i : IN std_logic_vector(3 downto 0); - m2_wb_we_i : IN std_logic; - m2_wb_dat_i : IN std_logic_vector(31 downto 0); - m2_wb_cyc_i : IN std_logic; - m2_wb_stb_i : IN std_logic; - s1_wb_ack_i : IN std_logic; - s1_wb_err_i : IN std_logic; - s1_wb_dat_i : IN std_logic_vector(31 downto 0); - s2_wb_ack_i : IN std_logic; - s2_wb_err_i : IN std_logic; - s2_wb_dat_i : IN std_logic_vector(31 downto 0); - m1_wb_dat_o : OUT std_logic_vector(31 downto 0); - m1_wb_ack_o : OUT std_logic; - m1_wb_err_o : OUT std_logic; - m2_wb_dat_o : OUT std_logic_vector(31 downto 0); - m2_wb_ack_o : OUT std_logic; - m2_wb_err_o : OUT std_logic; - s1_wb_adr_o : OUT std_logic_vector(31 downto 0); - s1_wb_sel_o : OUT std_logic_vector(3 downto 0); - s1_wb_we_o : OUT std_logic; - s1_wb_cyc_o : OUT std_logic; - s1_wb_stb_o : OUT std_logic; - s1_wb_dat_o : OUT std_logic_vector(31 downto 0); - s2_wb_adr_o : OUT std_logic_vector(31 downto 0); - s2_wb_sel_o : OUT std_logic_vector(3 downto 0); - s2_wb_we_o : OUT std_logic; - s2_wb_cyc_o : OUT std_logic; - s2_wb_stb_o : OUT std_logic; - s2_wb_dat_o : OUT std_logic_vector(31 downto 0) +component icon +port ( + control0 : out std_logic_vector(35 downto 0) ); -END COMPONENT; +end component; + +component ila +port ( + control : in std_logic_vector(35 downto 0); + clk : in std_logic; + data : in std_logic_vector(63 downto 0); + trig0 : in std_logic_vector(31 downto 0) + ); +end component; + +component phydcm is +port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end component; signal pci_rst_o : std_logic; signal pci_rst_oe_o : std_logic; @@ -248,10 +230,16 @@ signal md_pad_o : std_logic; signal md_padoe_o : std_logic; signal int_o : std_logic; signal wbm_adr_o : std_logic_vector(31 downto 0); +signal mdc_pad_o_watch : std_logic; signal m_wb_cti_o : std_logic_vector(2 downto 0); signal m_wb_bte_o : std_logic_vector(1 downto 0); +signal control0 : std_logic_vector(35 downto 0); +signal data : std_logic_vector(63 downto 0); +signal trig0 : std_logic_vector(31 downto 0); + + BEGIN PCI_RSTn <= pci_rst_o when (pci_rst_oe_o = '1') else 'Z'; @@ -275,7 +263,28 @@ BLA2: FOR i in 3 downto 0 generate PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z'; end generate; -wb_adr_i <= wbm_adr_o (11 downto 2); +wb_adr_i(11 downto 8) <= (others => '0'); +wb_adr_i(7 downto 2) <= wbm_adr_o (7 downto 2); + +wb_clk_i <= PCI_CLOCK; + +data(31 downto 0) <= wbm_adr_o; +data(39 downto 32) <= wbm_adr_o (7 downto 0); +data(40) <= MD_PAD_IO; +data(41) <= md_pad_o; +data(42) <= md_padoe_o; +data(43) <= mdc_pad_o_watch; +data(44) <= pci_inta_o; +MDC_PAD_O <= mdc_pad_o_watch; +data(63 downto 45) <= (others => '0'); + +trig0(31 downto 0) <= ( + 0 => wb_stb_i, + 1 => MD_PAD_IO, + 2 => md_pad_o, + 3 => md_padoe_o, + others => '0' +); Inst_pci_bridge32: pci_bridge32 PORT MAP( wb_clk_i => wb_clk_i , @@ -358,7 +367,7 @@ Inst_eth_top: eth_top PORT MAP( wb_sel_i => wb_sel_i , wb_we_i => wb_we_i , wb_cyc_i => wb_cyc_i , - wb_stb_i => wb_stb_i , + wb_stb_i => wb_stb_i, wb_ack_o => wb_ack_o , wb_err_o => wb_err_o , m_wb_adr_o => m_wb_adr_o, @@ -380,7 +389,7 @@ Inst_eth_top: eth_top PORT MAP( mrxerr_pad_i => MRXERR_PAD_I, mcoll_pad_i => MCOLL_PAD_I, mcrs_pad_i => MCRS_PAD_I, - mdc_pad_o => MDC_PAD_O, + mdc_pad_o => mdc_pad_o_watch, md_pad_i => MD_PAD_IO, md_pad_o => md_pad_o, md_padoe_o => md_padoe_o, @@ -389,45 +398,26 @@ Inst_eth_top: eth_top PORT MAP( int_o => int_o ); ---Inst_eth_cop: eth_cop PORT MAP( --- wb_clk_i => , --- wb_rst_i => , --- m1_wb_adr_i => , --- m1_wb_sel_i => , --- m1_wb_we_i => , --- m1_wb_dat_o => , --- m1_wb_dat_i => , --- m1_wb_cyc_i => , --- m1_wb_stb_i => , --- m1_wb_ack_o => , --- m1_wb_err_o => , --- m2_wb_adr_i => , --- m2_wb_sel_i => , --- m2_wb_we_i => , --- m2_wb_dat_o => , --- m2_wb_dat_i => , --- m2_wb_cyc_i => , --- m2_wb_stb_i => , --- m2_wb_ack_o => , --- m2_wb_err_o => , --- s1_wb_adr_o => , --- s1_wb_sel_o => , --- s1_wb_we_o => , --- s1_wb_cyc_o => , --- s1_wb_stb_o => , --- s1_wb_ack_i => , --- s1_wb_err_i => , --- s1_wb_dat_i => , --- s1_wb_dat_o => , --- s2_wb_adr_o => , --- s2_wb_sel_o => , --- s2_wb_we_o => , --- s2_wb_cyc_o => , --- s2_wb_stb_o => , --- s2_wb_ack_i => , --- s2_wb_err_i => , --- s2_wb_dat_i => , --- s2_wb_dat_o => ---); +i_icon : icon +port map ( + control0 => control0 + ); + +i_ila : ila +port map ( + control => control0, + clk => PCI_CLOCK, + data => data, + trig0 => trig0 + ); + +eth_dcm : phydcm +port map ( + CLKIN_IN => PCI_CLOCK, + RST_IN => not PCI_RSTn, + CLKFX_OUT => PHY_CLOCK, + CLK0_OUT => open, + LOCKED_OUT => open + ); end architecture ethernet_arch;