X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/7a6a1ff70fc526bd7f7feacdf2f25ee77f779260..ac5b827129ac002c0b2caa0d822868383c1416f2:/ethernet/source/phydcm.vhd

diff --git a/ethernet/source/phydcm.vhd b/ethernet/source/phydcm.vhd
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+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
+--------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 9.1.02i
+--  \   \         Application : xaw2vhdl
+--  /   /         Filename : phydcm.vhd
+-- /___/   /\     Timestamp : 03/21/2007 14:47:39
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--Command: xaw2vhdl-st phydcm.xaw phydcm
+--Design Name: phydcm
+--Device: xc3s1500-fg456-4
+--
+-- Module phydcm
+-- Generated by Xilinx Architecture Wizard
+-- Written for synthesis tool: XST
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+
+entity phydcm is
+   port ( CLKIN_IN        : in    std_logic; 
+          RST_IN          : in    std_logic; 
+          CLKFX_OUT       : out   std_logic; 
+          CLKIN_IBUFG_OUT : out   std_logic; 
+          CLK0_OUT        : out   std_logic; 
+          LOCKED_OUT      : out   std_logic);
+end phydcm;
+
+architecture BEHAVIORAL of phydcm is
+   signal CLKFB_IN        : std_logic;
+   signal CLKFX_BUF       : std_logic;
+   signal CLKIN_IBUFG     : std_logic;
+   signal CLK0_BUF        : std_logic;
+   signal GND_BIT         : std_logic;
+   component BUFG
+      port ( I : in    std_logic; 
+             O : out   std_logic);
+   end component;
+   
+   component IBUFG
+      port ( I : in    std_logic; 
+             O : out   std_logic);
+   end component;
+   
+   -- Period Jitter (unit interval) for block DCM_INST = 0.06 UI
+   -- Period Jitter (Peak-to-Peak) for block DCM_INST = 2.27 ns
+   component DCM
+      generic( CLK_FEEDBACK : string :=  "1X";
+               CLKDV_DIVIDE : real :=  2.0;
+               CLKFX_DIVIDE : integer :=  1;
+               CLKFX_MULTIPLY : integer :=  4;
+               CLKIN_DIVIDE_BY_2 : boolean :=  FALSE;
+               CLKIN_PERIOD : real :=  10.0;
+               CLKOUT_PHASE_SHIFT : string :=  "NONE";
+               DESKEW_ADJUST : string :=  "SYSTEM_SYNCHRONOUS";
+               DFS_FREQUENCY_MODE : string :=  "LOW";
+               DLL_FREQUENCY_MODE : string :=  "LOW";
+               DUTY_CYCLE_CORRECTION : boolean :=  TRUE;
+               FACTORY_JF : bit_vector :=  x"C080";
+               PHASE_SHIFT : integer :=  0;
+               STARTUP_WAIT : boolean :=  FALSE;
+               DSS_MODE : string :=  "NONE");
+      port ( CLKIN    : in    std_logic; 
+             CLKFB    : in    std_logic; 
+             RST      : in    std_logic; 
+             PSEN     : in    std_logic; 
+             PSINCDEC : in    std_logic; 
+             PSCLK    : in    std_logic; 
+             DSSEN    : in    std_logic; 
+             CLK0     : out   std_logic; 
+             CLK90    : out   std_logic; 
+             CLK180   : out   std_logic; 
+             CLK270   : out   std_logic; 
+             CLKDV    : out   std_logic; 
+             CLK2X    : out   std_logic; 
+             CLK2X180 : out   std_logic; 
+             CLKFX    : out   std_logic; 
+             CLKFX180 : out   std_logic; 
+             STATUS   : out   std_logic_vector (7 downto 0); 
+             LOCKED   : out   std_logic; 
+             PSDONE   : out   std_logic);
+   end component;
+   
+begin
+   GND_BIT <= '0';
+   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
+   CLK0_OUT <= CLKFB_IN;
+   CLKFX_BUFG_INST : BUFG
+      port map (I=>CLKFX_BUF,
+                O=>CLKFX_OUT);
+   
+   CLKIN_IBUFG_INST : IBUFG
+      port map (I=>CLKIN_IN,
+                O=>CLKIN_IBUFG);
+   
+   CLK0_BUFG_INST : BUFG
+      port map (I=>CLK0_BUF,
+                O=>CLKFB_IN);
+   
+   DCM_INST : DCM
+   generic map( CLK_FEEDBACK => "1X",
+            CLKDV_DIVIDE => 2.0,
+            CLKFX_DIVIDE => 29,
+            CLKFX_MULTIPLY => 22,
+            CLKIN_DIVIDE_BY_2 => FALSE,
+            CLKIN_PERIOD => 30.303,
+            CLKOUT_PHASE_SHIFT => "NONE",
+            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
+            DFS_FREQUENCY_MODE => "LOW",
+            DLL_FREQUENCY_MODE => "LOW",
+            DUTY_CYCLE_CORRECTION => TRUE,
+            FACTORY_JF => x"8080",
+            PHASE_SHIFT => 0,
+            STARTUP_WAIT => FALSE)
+      port map (CLKFB=>CLKFB_IN,
+                CLKIN=>CLKIN_IBUFG,
+                DSSEN=>GND_BIT,
+                PSCLK=>GND_BIT,
+                PSEN=>GND_BIT,
+                PSINCDEC=>GND_BIT,
+                RST=>RST_IN,
+                CLKDV=>open,
+                CLKFX=>CLKFX_BUF,
+                CLKFX180=>open,
+                CLK0=>CLK0_BUF,
+                CLK2X=>open,
+                CLK2X180=>open,
+                CLK90=>open,
+                CLK180=>open,
+                CLK270=>open,
+                LOCKED=>LOCKED_OUT,
+                PSDONE=>open,
+                STATUS=>open);
+   
+end BEHAVIORAL;
+
+