X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/7a6a1ff70fc526bd7f7feacdf2f25ee77f779260..ac5b827129ac002c0b2caa0d822868383c1416f2:/ethernet/source/top.vhd

diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd
index 611e9c0..480de0a 100644
--- a/ethernet/source/top.vhd
+++ b/ethernet/source/top.vhd
@@ -171,6 +171,15 @@ port (
 	);
 end component;
 
+component phydcm is
+port ( CLKIN_IN        : in    std_logic;
+       RST_IN          : in    std_logic;
+       CLKFX_OUT       : out   std_logic;
+       CLKIN_IBUFG_OUT : out   std_logic;
+       CLK0_OUT        : out   std_logic;
+       LOCKED_OUT      : out   std_logic);
+end component;
+
 signal pci_rst_o : std_logic;
 signal pci_rst_oe_o : std_logic;
 signal pci_inta_o : std_logic;
@@ -258,7 +267,6 @@ wb_adr_i(11 downto 8) <= (others => '0');
 wb_adr_i(7 downto 2)  <= wbm_adr_o (7 downto 2);
 
 wb_clk_i <= PCI_CLOCK;
-PHY_CLOCK <= PCI_CLOCK;
 
 data(31 downto 0)  <= wbm_adr_o;
 data(40 downto 33) <= wbm_adr_o (7 downto 0);
@@ -394,4 +402,14 @@ port map (
 	trig0 => trig0
 	);
 
+eth_dcm : phydcm
+port map (
+	CLKIN_IN => PCI_CLOCK,
+	RST_IN => not PCI_RSTn,
+	CLKFX_OUT => PHY_CLOCK
+--	CLKIN_IBUFG_OUT
+--	CLK0_OUT
+--	LOCKED_OUT
+	);
+
 end architecture ethernet_arch;