X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/7b50ad38e2051140636e809d88fa4f6667ef0279..7e85e64823c67c08644df189e8a503a9b0409f1a:/dhwk_old/source/top_dhwk.vhd

diff --git a/dhwk_old/source/top_dhwk.vhd b/dhwk_old/source/top_dhwk.vhd
index dbb54e9..5345dce 100644
--- a/dhwk_old/source/top_dhwk.vhd
+++ b/dhwk_old/source/top_dhwk.vhd
@@ -1,43 +1,8 @@
---+-------------------------------------------------------------------------------------------------+
---|																									|
---|  File:			top.vhd                       		                                   	|
---|																									|
---|  Components:	pci32lite.vhd                                                                   |
---|		            pciwbsequ.vhd           														|
---|		            pcidmux.vhd           															|
---|		            pciregs.vhd           															|
---|		            pcipargen.vhd          															|
---|		            -- Libs --             															|
---|		            ona.vhd		          															|
---|																									|
---|	 Description:	RS1 PCI Demo : (TOP) Main file.						 				        |
---| 				 																				|
---|					                														        |
---|																									|
---+-------------------------------------------------------------------------------------------------+
---|																									|
---|  Revision history :																				|
---|  Date 		  Version	Author	Description														|
---|																									|
---|																									|
---|  To do:																 							|
---|																									|
---+-------------------------------------------------------------------------------------------------+
-
-
---+-----------------------------------------------------------------------------+
---|									LIBRARIES									|
---+-----------------------------------------------------------------------------+
-
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
---+-----------------------------------------------------------------------------+
---|									ENTITY   									|
---+-----------------------------------------------------------------------------+
-
 entity dhwk is
 port (
 
@@ -69,17 +34,9 @@ port (
 end dhwk;
 
 
---+-----------------------------------------------------------------------------+
---|									ARCHITECTURE								|
---+-----------------------------------------------------------------------------+
-
 architecture dhwk_arch of dhwk is
 
 
---+-----------------------------------------------------------------------------+
---|									COMPONENTS									|
---+-----------------------------------------------------------------------------+
-
 component pci32tlite
 port (
 
@@ -152,32 +109,44 @@ port (
 );
 end component;
 
+component wb_fifo
+port (
+	clk_i		: in std_logic;
+	nrst_i		: in std_logic;
+	
+	wb_adr_i	: in std_logic_vector(24 downto 1);
+	wb_dat_o	: out std_logic_vector(15 downto 0);
+	wb_dat_i	: in std_logic_vector(15 downto 0);
+	wb_sel_i	: in std_logic_vector(1 downto 0);
+	wb_we_i		: in std_logic;
+	wb_stb_i	: in std_logic;
+	wb_cyc_i	: in std_logic;
+	wb_ack_o	: out std_logic;
+	wb_err_o	: out std_logic;
+	wb_int_o	: out std_logic;
+	
+	fifo_data_i	: in std_logic_vector(7 downto 0);
+	fifo_data_o     : out std_logic_vector(7 downto 0);
+
+	fifo_we_out	: out std_logic;
+	fifo_re_out	: out std_logic
+);
+end component;
 
---+-----------------------------------------------------------------------------+
---|									CONSTANTS  									|
---+-----------------------------------------------------------------------------+
---+-----------------------------------------------------------------------------+
---|									SIGNALS   									|
---+-----------------------------------------------------------------------------+
-
-	signal 	wb_adr :		std_logic_vector(24 downto 1);   
-	signal	wb_dat_out :	std_logic_vector(15 downto 0);
- 	signal 	wb_dat_in :		std_logic_vector(15 downto 0);
-	signal	wb_sel :		std_logic_vector(1 downto 0);
- 	signal  wb_we :			std_logic;
-	signal	wb_stb :		std_logic;
-	signal	wb_cyc :		std_logic;
-	signal	wb_ack :		std_logic;
-	signal	wb_err :		std_logic;
-	signal	wb_int :		std_logic;
+signal 	wb_adr :		std_logic_vector(24 downto 1);   
+signal	wb_dat_out :	std_logic_vector(15 downto 0);
+signal 	wb_dat_in :		std_logic_vector(15 downto 0);
+signal	wb_sel :		std_logic_vector(1 downto 0);
+signal  wb_we :			std_logic;
+signal	wb_stb :		std_logic;
+signal	wb_cyc :		std_logic;
+signal	wb_ack :		std_logic;
+signal	wb_err :		std_logic;
+signal	wb_int :		std_logic;
 
 
 begin
 
---+-----------------------------------------+
---|  PCI Target 							|
---+-----------------------------------------+
-
 u_pci: component pci32tlite
 port map(
     	clk33 =>		PCI_CLK,
@@ -208,10 +177,6 @@ port map(
 --		debug_access =>	LED2
 		);
 
---+-----------------------------------------+
---|  WB-7seg             					|
---+-----------------------------------------+
-
 my_heartbeat: component heartbeat
 port map( 
 	clk_i => PCI_CLK,