X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/7c54167d1f3a37b18f51ebe28d8820f04438bbc4..3c76f814e51b2574a0cdc5dc3dc5710f31fbc443:/dhwk/source/pci/pci_interface.vhd diff --git a/dhwk/source/pci/pci_interface.vhd b/dhwk/source/pci/pci_interface.vhd index 722cce6..d15f9da 100644 --- a/dhwk/source/pci/pci_interface.vhd +++ b/dhwk/source/pci/pci_interface.vhd @@ -109,12 +109,6 @@ architecture SCHEMATIC of PCI_INTERFACE is SERR : Out std_logic ); end component; - component VERGLEICH - Port ( IN_A : In std_logic_vector (31 downto 0); - IN_B : In std_logic_vector (31 downto 0); - GLEICH_OUT : Out std_logic ); - end component; - component IO_MUX_REG Port ( CONFIG_DATA : In std_logic_vector (31 downto 0); LOAD_ADDR_REG : In std_logic; @@ -189,10 +183,6 @@ begin SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8), PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn, PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR ); - I4 : VERGLEICH - Port Map ( IN_A(31 downto 0)=>CONF_DATA_10H(31 downto 0), - IN_B(31 downto 0)=>AD_REG_DUMMY(31 downto 0), - GLEICH_OUT=>MY_ADDR ); I2 : IO_MUX_REG Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0), LOAD_ADDR_REG=>LAR, @@ -222,4 +212,17 @@ begin CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0), CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) ); + process (PCI_CLOCK,PCI_RSTn) + begin + if PCI_RSTn = '0' then + MY_ADDR <= '0'; + + elsif (rising_edge(PCI_CLOCK)) then + if (CONF_DATA_10H(31 downto 2) = ADDR_REG_DUMMY(31 downto 2)) then + MY_ADDR <= '1'; + else + MY_ADDR <= '0'; + end if; + end if; + end process; end SCHEMATIC;