X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/raggedstone/blobdiff_plain/7f64ffff4404505290147b02b80d22dcd0e2de65..2e92b1a116510750a30acf463cbe53ef2f0e8648:/dhwk/source/pci/config_space_header.vhd

diff --git a/dhwk/source/pci/config_space_header.vhd b/dhwk/source/pci/config_space_header.vhd
index 0b98174..363e4c1 100644
--- a/dhwk/source/pci/config_space_header.vhd
+++ b/dhwk/source/pci/config_space_header.vhd
@@ -112,9 +112,6 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
         signal CONFIG_ADDR :std_logic_vector(7 downto 0);
         signal CONFIG_WRITE :std_logic_vector(3 downto 0);
 
-        ----
-        ----
-
         SIGNAL gnd : std_logic := '0';
         SIGNAL vcc : std_logic := '1';
 
@@ -122,17 +119,10 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
         signal CONF_WR_10H : std_logic;
         signal CONF_WR_3CH : std_logic;
         signal CONF_READ_SEL : std_logic_vector (2 downto 0);
-        signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
         signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
         signal CONF_DATA_08H : std_logic_vector (31 downto 0);
         signal CONF_DATA_00H : std_logic_vector (31 downto 0);
 
-        component CONFIG_RD_0
-                Port ( ADDR_REG : In std_logic_vector (31 downto 0);
-                       CF_RD_COM : In std_logic;
-                       READ_SEL : Out std_logic_vector (2 downto 0) );
-        end component;
-
 begin
         CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
         CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
@@ -152,11 +142,6 @@ begin
         CONF_BAS_ADDR_REG(3 downto 2) <= "00";-- IO Bereich = 16 BYTE
         CONF_DATA_10H <= CONF_BAS_ADDR_REG;
 
-        I9 : CONFIG_RD_0
-        Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
-                   CF_RD_COM=>CF_RD_COM,
-                   READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );
-
         process (PCI_CLOCK,PCI_RSTn)
         begin
         if PCI_RSTn = '0' then
@@ -328,4 +313,34 @@ begin
         CONF_WR_3CH <= CONFIG_WRITE(2);
         --CONF_WR_40H <= CONFIG_WRITE(3);
 
+        process (CF_RD_COM, CONFIG_ADDR)
+        begin
+
+                if CF_RD_COM = '1' then
+                        if CONFIG_ADDR = X"00" then
+                                CONF_READ_SEL <= "000";
+
+                        elsif CONFIG_ADDR = X"04" then
+                                CONF_READ_SEL <= "001";
+
+                        elsif CONFIG_ADDR = X"08" then
+                                CONF_READ_SEL <= "010";
+
+                        elsif CONFIG_ADDR = X"10" then
+                                CONF_READ_SEL <= "011";
+
+                        elsif CONFIG_ADDR = X"3C" then
+                                CONF_READ_SEL <= "100";
+
+                        elsif CONFIG_ADDR = X"40" then
+                                CONF_READ_SEL <= "101";
+
+                        else
+                                CONF_READ_SEL <= "111";
+                        end if;
+                else
+                        CONF_READ_SEL <= "111";
+                end if;
+        end process;
+
 end SCHEMATIC;